US4617477A
Expired / Lapsed
US
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Symmetrical output complementary buffer
Assignee: Nokia Bell Labs
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Filing: 1985-05-21
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Granted: 1986-10-14
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Expires: 2005-05-21
Abstract
Abstract A circuit generates complementary output signals which occur essentially simultaneously to each other. The circuit comprises three inverting and one non-inverting pairs of complementary transistors, typically field effect types. One of the inverting pairs provides the circuit inverted output. The output of the non-inverting pair is coupled to the output of another of the inverting pairs, which provide the circuit non-inverted output. In this manner, full Vss to Vcc output levels are achieved for substantially symmetrical output signals.
Inventors
- 👤 Michael V. DePaolis, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:51
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/151; H03K19/00; H03K19/003; H03K19/00315; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
212 words
Circuitry comprising: first, second, third, fourth, fifth, and sixth transistors T21, T22, T23, T24, T27, and T28, respectively, each having a control electrode and first and second output electrodes; T21, T24, and T27 being of a first conductivity type, and T22, T23 and T28 being of the opposite conductivity type; the control electrodes of T21, T22, T23 and T24 being coupled together to a circuitry input node; the second output electrode of T21 being coupled to the second output electrode of T22 and to a first circuitry output node; the control electrodes of T27 and T28 being coupled to an intermediate node which is characterized to be at a potential level that is the inverse of the level applied to the circuitry input node; the first output electrodes of T23 and T24 being coupled to the second output electrodes of T27 and T28 and to a second circuitry output node; the first output electrodes of T21 and T27, and the second output electrode of T23, being adapted to be coupled to a first potential source; and the first output electrodes of T22 and T28, and the second output electrode of T24, being adapted to be coupled to a second potential source which has a different potential level than the first potential source.
Claim 2
Dependent Claim
212 words
Circuitry comprising: first, second, third, fourth, fifth, and sixth transistors T21, T22, T23, T24, T27, and T28, respectively, each having a control electrode and first and second output electrodes; T21, T24, and T27 being of a first conductivity type, and T22, T23 and T28 being of the opposite conductivity type; the control electrodes of T21, T22, T23 and T24 being coupled together to a circuitry input node; the second output electrode of T21 being coupled to the second output electrode of T22 and to a first circuitry output node; the control electrodes of T27 and T28 being coupled to an intermediate node which is characterized to be at a potential level that is the inverse of the level applied to the circuitry input node; the first output electrodes of T23 and T24 being coupled to the second output electrodes of T27 and T28 and to a second circuitry output node; the first output electrodes of T21 and T27, and the second output electrode of T23, being adapted to be coupled to a first potential source; and the first output electrodes of T22 and T28, and the second output electrode of T24, being adapted to be coupled to a second potential source which has a different potential level than the first potential source.
Claim 3
Dependent Claim
42 words
Circuitry of claim 1 wherein: T21, T24, and T27 are p-channel field effect transistors, and T22, T23, and T28 are n-channel field effect transistors; wherein said first output electrodes thereof are source electrodes, and said second output electrodes thereof are drain electrodes.
Claim 4
Dependent Claim
18 words
Circuitry of claim 2 wherein: T21, T22, T23, T24, T27, and T28 are insulated gate field effect transistors.
Claim 5
Dependent Claim
32 words
Circuitry of claim 1 wherein: when the circuitry is in operation, said first circuitry output node and said second circuitry output node are characterized to produce simultaneous complementary full output potential levels.
Claim 6
Dependent Claim
204 words
Circuitry comprising: first, second, third, fourth, fifth, sixth, seventh and eighth field effect transistors T21, T22, T23, T24, T25, T26, T27 and T28, respectively, each having a gate electrode, a source electrode, and a drain electrode; T21, T24, T25 and T27 being of a first conductivity type, and T22, T23, T26 and T28 being of the opposite conductivity type; the gate electrodes of T21, T22, T23, T24, T25, and T26 being coupled together to an input circuitry node; the drain electrode of T21 being coupled to the drain electrode of T22 and to a first circuitry output node; the drain electrode of T25 being coupled to the drain electrode of T26 and to the gate electrodes of T27 and T28; the source electrodes of T23 and T24 being coupled to the drain electrodes of T27 and T28 and to a second output circuitry node; the source electrodes of T21, T25, and T27, and the drain electrode of T23, being adapted to be coupled to a first potential source; and the source electrodes of T22, T26, and T28, and the drain electrode of T24, being adapted to be coupled to a second potential source which has a different potential level than the first potential source.
Claim 7
Dependent Claim
204 words
Circuitry comprising: first, second, third, fourth, fifth, sixth, seventh and eighth field effect transistors T21, T22, T23, T24, T25, T26, T27 and T28, respectively, each having a gate electrode, a source electrode, and a drain electrode; T21, T24, T25 and T27 being of a first conductivity type, and T22, T23, T26 and T28 being of the opposite conductivity type; the gate electrodes of T21, T22, T23, T24, T25, and T26 being coupled together to an input circuitry node; the drain electrode of T21 being coupled to the drain electrode of T22 and to a first circuitry output node; the drain electrode of T25 being coupled to the drain electrode of T26 and to the gate electrodes of T27 and T28; the source electrodes of T23 and T24 being coupled to the drain electrodes of T27 and T28 and to a second output circuitry node; the source electrodes of T21, T25, and T27, and the drain electrode of T23, being adapted to be coupled to a first potential source; and the source electrodes of T22, T26, and T28, and the drain electrode of T24, being adapted to be coupled to a second potential source which has a different potential level than the first potential source.
Claim 8
Dependent Claim
20 words
Circuitry of claim 5 wherein: T21, T22, T23, T24, T25, T26, T27 and T28 are insulated gate field effect transistors.
Claim 9
Dependent Claim
22 words
Circuitry of claim 6 wherein: T21, T24, T25 and T27 are p-channel transistors, and T22, T23, T26 and T28 are n-channel transistors.
Claim 10
Dependent Claim
26 words
Cicuitry of claim 5 wherein: when the circuitry is in operation, its first and second output nodes are characterized to produce simultaneous complementary full potential levels.
Claim 11
Dependent Claim
131 words
Circuitry compising: first, second, and third inverting pairs of complementary field effect transistors, and a non-inverting pair of complementary field effect transistors, with each pair having an input node and an output node, the transistors of each pair being serially coupled together; a circuitry input node coupled to the input node of each of the first and second inverting pairs, and the non-inverting pair of transistors; the output node of the second inverting pair of transistors being coupled to the input node of the third inverting pair of transistors; a first circuitry output node being coupled to the output node of the first inverting pair of transistors; a second circuitry output node being coupled to the output node of each of the third inverting pair and the non-inverting pair of transistors.
Claim 12
Dependent Claim
131 words
Circuitry compising: first, second, and third inverting pairs of complementary field effect transistors, and a non-inverting pair of complementary field effect transistors, with each pair having an input node and an output node, the transistors of each pair being serially coupled together; a circuitry input node coupled to the input node of each of the first and second inverting pairs, and the non-inverting pair of transistors; the output node of the second inverting pair of transistors being coupled to the input node of the third inverting pair of transistors; a first circuitry output node being coupled to the output node of the first inverting pair of transistors; a second circuitry output node being coupled to the output node of each of the third inverting pair and the non-inverting pair of transistors.
Claim 13
Dependent Claim
105 words
Circuitry comprising: an input node adapted to receive an input signal; a first pair of inverting complementary transistors having an input connected to said input node and an output connected to an inverted output node; a second pair of inverting complementary transistors having an input connected to said input node and having an output adapted to provide an inverted signal to the input of a third pair of inverting complementary transistors having an output connected to a non-inverted output node; and a pair of non-inverting complementary transistors having an input connected to said input node and having an output connected to said non-inverted output node.
Claim 14
Dependent Claim
105 words
Circuitry comprising: an input node adapted to receive an input signal; a first pair of inverting complementary transistors having an input connected to said input node and an output connected to an inverted output node; a second pair of inverting complementary transistors having an input connected to said input node and having an output adapted to provide an inverted signal to the input of a third pair of inverting complementary transistors having an output connected to a non-inverted output node; and a pair of non-inverting complementary transistors having an input connected to said input node and having an output connected to said non-inverted output node.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-13 | 1990-04-14 | 1990-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-13 | 1994-04-14 | 1994-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-13 | 1998-04-14 | 1998-10-14 | $7700.00 | Window Closed / Lapsed |