Complementary field-effect transistor buffer circuit

Claim 2

The combination comprising: first, second, third junction points and an output point; an inverter having an input terminal and an output terminal coupled between said first and second junction points; first and second transistors of one conductivity type and a third transistor of second conductivity type; each transistor having first and second electrodes defining the ends of a conduction path and a control electrode; means coupling the conduction path of said first and third transistors in parallel between said third junction point and said output point; means coupling said second transistor between said output point and said second junction point; and means coupling the control electrodes of said second and third transistors in common to one of said input and output terminals of said inverter, and the control electrode of said first transistor to the other one of said input and output terminals of said inverter.

Claim 3

The combination as claimed in claim 1, wherein said transistors are insulated-gate field-effect transistors of the enhancement type and wherein said inverter is a complementary inverter.

Claim 4

A first voltage of given amplitude to be applied to said first junction point; and

Claim 5

A first voltage of given amplitude to be applied to said first junction point; and

Claim 6

A second voltage to be applied to said third junction point, said second voltage having a voltage level at most equal to said first voltage.

Claim 7

A second voltage to be applied to said third junction point, said second voltage having a voltage level at most equal to said first voltage.

Claim 8

The combination as claimed in claim 1, further including at least one source of potential to provide:

Claim 9

The combination as claimed in claim 3, further providing means for coupling a source of signal to said input of said inverter; said signal source providing signals having one of a first value substantially equal to said reference potential and a second value substantially equal in amplitude to said first voltage level; in response to the application of said signals the signals at said output point take on one of a first and second value said first value being substantially equal to said reference potential and said second value being substantially equal in amplitude to said second voltage level.

Claim 10

The combination as claimed in claim 3, further providing means for coupling load means having a signal input point, and responsive to signals applied to said signal input point, to said output point; said load means also having two terminals for the application thereto of an operating potential wherein a potential equal to said second voltage is applied to one terminal and said reference potential is applied to the other of said two terminals.

Claim 11

The combination as claimed in claim 3, wherein said transistors are of the type that the voltage applied to the control electrode must exceed a given value defined as the threshold voltage before conduction can occur; and wherein the voltage level of said second voltage is variable and may have a lower limit whose value is below the value of the threshold voltage of said third transistor.

Claim 12

A Buffer circuit comprising: first and second junction points and input and output points; first and second transistors of one conductivity type and a third transistor of second conductivity type; each transistor having source and drain electrodes defining the ends of a conduction path and a control electrode; means coupling the conduction paths of said first and third transistors in parallel between said first junction point and said output point to form a first clamping circuit; means coupling said second transistor between said output point and said second junction point to form a second clamping circuit; and signal generating means responsive to input signals applied to said input point suitable to enable one of said first and second clamping circuits thereby clamping said output point to one of said first and second junction points.

Claim 13

A Buffer circuit comprising: first and second junction points and input and output points; first and second transistors of one conductivity type and a third transistor of second conductivity type; each transistor having source and drain electrodes defining the ends of a conduction path and a control electrode; means coupling the conduction paths of said first and third transistors in parallel between said first junction point and said output point to form a first clamping circuit; means coupling said second transistor between said output point and said second junction point to form a second clamping circuit; and signal generating means responsive to input signals applied to said input point suitable to enable one of said first and second clamping circuits thereby clamping said output point to one of said first and second junction points.

Claim 14

The combination as claimed in claim 7, further providing a source of operating potential having first and reference voltage levels applied respectively to said first and second junction points; and wherein said input signals have an amplitude equal to or greater than said first voltage level with respect to said reference voltage.

Claim 15

The combination as claimed in claim 8, wherein said first transistor is operated in the source follower mode and wherein said second and third transistors are operated in the common source mode.

Claim 16

For use with a circuit which includes a load having an input terminal to which it is desired to apply a signal of an amplitude not greater than a first voltage and which includes a field-effect transistor driving circuit supplying a signal whose amplitude may exceed said first voltage, a buffer circuit comprising, in combination: a first terminal at said first voltage and a second terminal at a point of reference potential; an output point for connecting said load input terminal thereto; a first clamping circuit, comprising a complementary transmission gate having first and second field-effect transistors of first and second conductivity type, respectively, whose conduction paths are connected in parallel, coupled between said first terminal and said output point, said first clamping circuit, when enabled, clamping said output point to said first voltage level; a second clamping circuit coupled between said output point and said second terminal for clamping, when enabled, said output point to said reference potential; and means responsive to said signal from said driving circuit for enabling one of said first and second clamping circuits.

Claim 17

For use with a circuit which includes a load having an input terminal to which it is desired to apply a signal of an amplitude not greater than a first voltage and which includes a field-effect transistor driving circuit supplying a signal whose amplitude may exceed said first voltage, a buffer circuit comprising, in combination: a first terminal at said first voltage and a second terminal at a point of reference potential; an output point for connecting said load input terminal thereto; a first clamping circuit, comprising a complementary transmission gate having first and second field-effect transistors of first and second conductivity type, respectively, whose conduction paths are connected in parallel, coupled between said first terminal and said output point, said first clamping circuit, when enabled, clamping said output point to said first voltage level; a second clamping circuit coupled between said output point and said second terminal for clamping, when enabled, said output point to said reference potential; and means responsive to said signal from said driving circuit for enabling one of said first and second clamping circuits.

Claim 18

The combination as claimed in claim 10, wherein said second clamping circuit includes a third field-effect transistor of first conductivity type; wherein each of said first, second, and third transistors has a control electrode and source and drain electrodes defining the ends of a conduction path; wherein the conduction paths of said first and second transistors are connected in parallel between said first terminal and said output point; and wherein the conduction path of said third transistor is connected between said output point and said second terminal.

Claim 19

A circuit for applying to an output terminal one of two different voltage levels comprising, in combination: a first terminal for receiving voltage at one of said levels; a second terminal for receiving voltage at the other of said levels; two transmission circuits connected in series between said first and second terminals, said output terminal being at the connection between said transmission circuits, said first transmission circuit comprising two conduction paths, in parallel, and said second transmission circuit comprising a single transmission path; and means responsive to an input signal in one voltage range for causing the two conduction paths in parallel to assume relatively high values of impedance and the single transmission path to assume a relatively low value of impedance, and responsive to an input signal in another voltage range for causing one, or the other, or both of the two conduction paths in parallel to assume a relatively low value of impedance, depending, in part, on the relative values of the input signal and said first vOltage level, and the single transmission path to assume a relatively high value of impedance.

Claim 20

A circuit for applying to an output terminal one of two different voltage levels comprising, in combination: a first terminal for receiving voltage at one of said levels; a second terminal for receiving voltage at the other of said levels; two transmission circuits connected in series between said first and second terminals, said output terminal being at the connection between said transmission circuits, said first transmission circuit comprising two conduction paths, in parallel, and said second transmission circuit comprising a single transmission path; and means responsive to an input signal in one voltage range for causing the two conduction paths in parallel to assume relatively high values of impedance and the single transmission path to assume a relatively low value of impedance, and responsive to an input signal in another voltage range for causing one, or the other, or both of the two conduction paths in parallel to assume a relatively low value of impedance, depending, in part, on the relative values of the input signal and said first vOltage level, and the single transmission path to assume a relatively high value of impedance.

Claim 21

A circuit for applying to an output terminal one of two different voltage levels comprising, in combination: a first terminal for receiving voltage at one level; a second terminal for receiving voltage at a second level; two transmission circuits connected in series between said first and second terminals, said output terminal being at the connection between said transmission circuits, said first transmission circuit comprising the conduction paths, in parallel, of first and second transistors of opposite conductivity type, and said second transmission circuit comprising the conduction path of a third transistor, said conduction paths being connected in the forward direction relative to said first and second voltage levels, and each said transistor including a control electrode to which a signal may be applied for controlling the conductivity of the conduction path of its transistor; and means responsive to an input signal in one range for applying signals to the control electrodes of said first and second transistors in a sense to cause their conduction paths to exhibit relatively high impedances and for applying a signal in the forward direction to the third transistor of an amplitude to cause its conduction path to assume a relatively low impedance, and responsive to an input signal in another range for applying signals in the forward direction to the control electrodes of said first and second transistors of an amplitude to cause at least one of the first and second paths to assume a relatively low value of impedance and applying a signal in the reverse direction to the third transistor for causing its conduction path to assume a relatively high impedance.

Claim 22

A circuit for applying to an output terminal one of two different voltage levels comprising, in combination: a first terminal for receiving voltage at one level; a second terminal for receiving voltage at a second level; two transmission circuits connected in series between said first and second terminals, said output terminal being at the connection between said transmission circuits, said first transmission circuit comprising the conduction paths, in parallel, of first and second transistors of opposite conductivity type, and said second transmission circuit comprising the conduction path of a third transistor, said conduction paths being connected in the forward direction relative to said first and second voltage levels, and each said transistor including a control electrode to which a signal may be applied for controlling the conductivity of the conduction path of its transistor; and means responsive to an input signal in one range for applying signals to the control electrodes of said first and second transistors in a sense to cause their conduction paths to exhibit relatively high impedances and for applying a signal in the forward direction to the third transistor of an amplitude to cause its conduction path to assume a relatively low impedance, and responsive to an input signal in another range for applying signals in the forward direction to the control electrodes of said first and second transistors of an amplitude to cause at least one of the first and second paths to assume a relatively low value of impedance and applying a signal in the reverse direction to the third transistor for causing its conduction path to assume a relatively high impedance.

Claim 23

A circuit for applying to an output terminal one of two different voltage levels comprising, in combination: a first terminal for receiving a voltage at one level; a second terminal for receiving voltage at a second level; two transmission circuits connected in series between said first and second terminals, said output terminal being at the connection between said transmission circuits, said first transmission circuit comprising the conduction paths in parallel of first and second transistors of opposite conductivity type, and said second transmission circuit comprising the conduction path of a third transistor, said conduction paths being connected in the forward direction relative to said first and second voltage levels; and means responsive to an input signal in one range for applying signals to the first and second transistors in a sense to drive them to cutoff and for applying a signal in the forward direction to the third transistor of an amplitude to cause its conduction path to assume a relatively low value of impedance, and responsive to an input signal in another range for applying signals in the forward direction to the first and second transistors of an amplitude to cause at least one of the first and second paths to assume a relatively low value of impedance and applying a signal in the reverse direction to the third transistor for driving it to cutoff.

Claim 24

A circuit for applying to an output terminal one of two different voltage levels comprising, in combination: a first terminal for receiving a voltage at one level; a second terminal for receiving voltage at a second level; two transmission circuits connected in series between said first and second terminals, said output terminal being at the connection between said transmission circuits, said first transmission circuit comprising the conduction paths in parallel of first and second transistors of opposite conductivity type, and said second transmission circuit comprising the conduction path of a third transistor, said conduction paths being connected in the forward direction relative to said first and second voltage levels; and means responsive to an input signal in one range for applying signals to the first and second transistors in a sense to drive them to cutoff and for applying a signal in the forward direction to the third transistor of an amplitude to cause its conduction path to assume a relatively low value of impedance, and responsive to an input signal in another range for applying signals in the forward direction to the first and second transistors of an amplitude to cause at least one of the first and second paths to assume a relatively low value of impedance and applying a signal in the reverse direction to the third transistor for driving it to cutoff.