Address buffer circuit with low power consumption

Claim 2

An address buffer circuit including: an inverter having an input for receiving an address signal, an output for providing an inversion signal being the inverted received address signal and a power source terminal for receiving power from a power source; a transistor connected in series between the power source terminal of the power source and having a gate electrode; a clock circuit, operatively connected to the gate electrode, for generating a first internal clock signal for turning ON the transistor only in a first time period and for generating a second internal clock signal at least during the first time period; a latch circuit operatively connected to the output of the inverter for latching the inversion signal in response to said second internal clock signal.

Claim 3

An address buffer circuit according to claim 1 wherein the clock circuit comprises: a transistor which operates on a signal inverted from an external clock signal to invert an output signal; a plurality of stages of inverters for delaying the second internal clock signal for the latch circuit, derived from the external clock signal; and a transistor for inverting the inverted output signal from the transistor by the output signal from the inverter.

Claim 4

An address buffer circuit including: an inverter having an input for receiving an address signal, an output for providing an inversion signal being the inverted received address signal and a power source terminal for receiving power from a power source; a first transistor connected in series between the power source terminal of the inverter and the power source and having a gate electrode; a second transistor connected between the output terminal of the inverter and ground and having a gate electrode; a clock circuit operatively connected to the gate electrodes of the first and second transistors, for generating a first internal clock signal, for turning ON the first transistor and for turning OFF the second transistor, only in a first time period and for generating a second internal clock signal at least during the first time period; a latch circuit operatively connected to the output of the inverter for latching the inversion signal in response to said second internal clock signal.

Claim 5

An address buffer circuit including: an inverter having an input for receiving an address signal, an output for providing an inversion signal being the inverted received address signal and a power source terminal for receiving power from a power source; a first transistor connected in series between the power source terminal of the inverter and the power source and having a gate electrode; a second transistor connected between the output terminal of the inverter and ground and having a gate electrode; a clock circuit operatively connected to the gate electrodes of the first and second transistors, for generating a first internal clock signal, for turning ON the first transistor and for turning OFF the second transistor, only in a first time period and for generating a second internal clock signal at least during the first time period; a latch circuit operatively connected to the output of the inverter for latching the inversion signal in response to said second internal clock signal.

Claim 6

An address buffer circuit according to claim 3, wherein the clock circuit comprises: an inverter operatively connected to receive an external clock signal, for providing a first output signal; first cascade connected inverter stages, one of said first cascade stages operatively connected to receive said first output signal, and at least one other of said first cascade stages providing as an output, said second internal clock signal; second cascade connected inverter stages for providing the first internal clock signal, one of said second cascade stages operatively connected to receive said second internal clock signal; a third transistor operatively connected between the output of the last stage of said second cascade stages and the power source, the third transistor being operatively connected to and controlled by said first output signal; a fourth transistor operatively connected in series between the last stage of said second cascade stages and ground, the third transistor being operatively connected to and controlled by said first output signal.