Triac having a multilayer semiconductor body

Claim 1

In a triac of the type in which a multilayer semiconductor body is arranged between first and second electrodes, in which there is a first thyristor and a second thyristor, a first, p-conductivity layer forms a base of the first thyristor and an emitter of the second thyristor, in which a second, n-conductivity layer forms bases for both thyristors, in which a third, p-conductivity layer forms an emitter of the first thyristor and a base of the second thyristor, in which a fourth, n-conductivity layer of the first thyristor is located in the first layer and contacts the first electrode, and in which a fifth, n-conductivity layer is located in the third layer and contacts the second electrode, the improvement therein comprising: an n-conductivity emitter region in the first layer adjacent and laterally spaced from the fourth layer in the direction of the second thyristor; a p-conductivity emitter region in the second layer laterally spaced from the first layer in the direction of the first thyristor; emitter electrodes contacting respective emitter regions; and gate-controlled metal-insulator-semiconductor structures at each of said n-conductivity and p-conductivity emitter regions, including gate-controlled short circuit paths, said short circuit paths bridging the pn junctions between said n-conductivity emitter region and said first layer and said p-conductivity emitter region and said second layer, respectively.

Claim 10

A method of operating a triac of the type in which a multilayer semiconductor body is arranged between first and second electrodes, in which there is a first thyristor and a second thyristor, in which a first, p-conductivity layer forms a base of the first thyristor and an emitter of the second thyristor, in which a second n-conductivity layer forms the bases for both thyristors, in which a third, p-conductivity layer forms an emitter of the first thyristor and a base of the second thyristor, in which a fourth, n-conductivity layer of the first thyristor is located in the first layer and contacts the first electrode, in which a fifth, n-conductivity layer is located in the third layer and contacts the second electrode, in which an n-conductivity emitter region is located in the first layer laterally spaced from the fourth layer, in which a p-conductivity emitter region is located in the second layer laterally spaced from the first layer, in which emitter electrodes contact respective emitter regions, in which gate-controlled metal-insulator-semiconductor structures are located at each of the n-conductivity and p-conductivity emitter regions and include gate-controlled short circuit paths, the short circuit paths bridging the pn junctions between said n-conductivity emitter region and said first layer and said p-conductivity emitter region and said second layer, respectively, in which the emitter regions are each divided into a plurality of strips, in which emitter electrodes are each divided into a plurality of portions and each contact a respective emitter region strip, in which a plurality of emitter short circuit paths is provided, each located adjacent an edge of an emitter region strip, in which a plurality of insulated gates are provided, each located over at least one edge of an emitter region and connected to a common gate terminal so that each thyristor has a respective common gate terminal, comprising the steps of: applying voltage pulses of a first polarity to the common gate terminal of the first thyristor; and applying voltage pulses of an opposite second polarity to the common gate terminal of the second thyristor.

Claim 11

A method of operating a triac of the type in which a multilayer semiconductor body is arranged between first and second electrodes, in which there is a first thyristor and a second thyristor, in which a first, p-conductivity layer forms a base of the first thyristor and an emitter of the second thyristor, in which a second n-conductivity layer forms the bases for both thyristors, in which a third, p-conductivity layer forms an emitter of the first thyristor and a base of the second thyristor, in which a fourth, n-conductivity layer of the first thyristor is located in the first layer and contacts the first electrode, in which a fifth, n-conductivity layer is located in the third layer and contacts the second electrode, in which an n-conductivity emitter region is located in the first layer laterally spaced from the fourth layer, in which a p-conductivity emitter region is located in the second layer laterally spaced from the first layer, in which emitter electrodes contact respective emitter regions, in which gate-controlled metal-insulator-semiconductor structures are located at each of the n-conductivity and p-conductivity emitter regions and include gate-controlled short circuit paths, the short circuit paths bridging the pn junctions between said n-conductivity emitter region and said first layer and said p-conductivity emitter region and said second layer, respectively, in which the emitter regions are each divided into a plurality of strips, in which emitter electrodes are each divided into a plurality of portions and each contact a respective emitter region strip, in which a plurality of emitter short circuit paths is provided, each located adjacent an edge of an emitter region strip, in which a plurality of insulated gates are provided, each located over at least one edge of an emitter region and connected to a common gate terminal so that each thyristor has a respective common gate terminal, comprising the steps of: applying voltage pulses of a first polarity to the common gate terminal of the first thyristor; and applying voltage pulses of an opposite second polarity to the common gate terminal of the second thyristor.