Planar four-layer-diode having a lateral arrangement of one of two partial transistors

Claim 2

A PLANAR FOUR-LAYER-DIODE HAVING A LATERAL ARRANGEMENT OF FIRST AND SECOND REGIONS FORMING A PARTIAL TRANSISTOR WHICH INCLUDES A SUBSTRATE OF ONE CONDUCTIVITY TYPE AND LATERALLY SPACED FIRST AND SECOND REGIONS OF OPPOSITE CONDUCTIVITY TYPE FORMING PN JUNCTIONS WITH SAID SUBSTRATE, AN INSULATING LAYER ABOVE SAID SUBSTRATE, A METAL ELECTRODE FORMED ON SAID INSULATING LAYER ABOVE THAT PORTION OF SAID SUBSTRATE BETWEEN THE PN JUNCTONS ONLY OF SAID LATERAL PARTIAL TRANSISTOR, AND METAL ELECTRODE BEING CONDUCTIVELY CONNECTED WITH SAID SUBSTRATE.

Claim 3

A planar four-layer-diode comprising a chip having a substrate of one impurity type having first and second impurity zones formed in said substrate of an opposite impurity type to said substrate, a portion of said substrate lying between said first and second impurity zones, a third impurity zone formed in said first impurity zone of the same impurity type as said substrate, a layer of insulating material formed on the upper surface of said chip overlying said first, second and third zones, and said portion of said substrate, first, second and third electrodes formed on said insulating layer and extending through said insulating layer into contact with said first, second and third zones, respectively, a fourth electrode overlying the undersurface of said substrate and in contact therewith, a fifth metal electrode overlying said insulating layer only above that said portion of said substrate which lies between said first and second impurity zones, and said fifth metal electrode being electrically connected to said substrate.

Claim 4

A planar four-layer-diode comprising a chip having a substrate of one impurity type having first and second impurity zones formed in said substrate of an opposite impurity type to said substrate, a portion of said substrate lying between said first and second impurity zones, a third impurity zone formed in said first impurity zone of the same impurity type as said substrate, a layer of insulating material formed on the upper surface of said chip overlying said first, second and third zones, and said portion of said substrate, first, second and third electrodes formed on said insulating layer and extending through said insulating layer into contact with said first, second and third zones, respectively, a fourth electrode overlying the undersurface of said substrate and in contact therewith, a fifth metal electrode overlying said insulating layer only above that said portion of said substrate which lies between said first and second impurity zones, and said fifth metal electrode being electrically connected to said substrate.

Claim 5

A diode according to claim 2, in which said fifth electrode extends laterally only as far as the space charge zones which are located adjacent the pn junctions between said portion of said substrate which lIes between said first and second impurity zones.

Claim 6

A planar four-layer-diode comprising a semiconductor substrate of one conductivity type, first and second regions of the opposite conductivity type in one surface thereof, the portion of said substrate lying between said first and second regions forming a third region which in conjunction with said first and second regions constitutes a partial lateral transistor, a fourth region of said one conductivity type in the surface of said first region; said fourth region, said first region, and said substrate forming a second partial transistor, an insulating layer on said substrate above said regions, a first, second and fourth metal electrode formed on said insulating layer above said first, second and fourth regions, said insulating layer having windows therethrough through which said first, second and fourth metal electrodes extend into contact with their associated regions, a third metal electrode on said insulating layer above said third region and only extending over the region which lies between the pn junctions of said first partial transistor, said third metal electrode being electrically connected to said substrate.

Claim 7

A planar four-layer-diode comprising a semiconductor substrate of one conductivity type, first and second regions of the opposite conductivity type in one surface thereof, the portion of said substrate lying between said first and second regions forming a third region which in conjunction with said first and second regions constitutes a partial lateral transistor, a fourth region of said one conductivity type in the surface of said first region; said fourth region, said first region, and said substrate forming a second partial transistor, an insulating layer on said substrate above said regions, a first, second and fourth metal electrode formed on said insulating layer above said first, second and fourth regions, said insulating layer having windows therethrough through which said first, second and fourth metal electrodes extend into contact with their associated regions, a third metal electrode on said insulating layer above said third region and only extending over the region which lies between the pn junctions of said first partial transistor, said third metal electrode being electrically connected to said substrate.

Claim 8

A planar four-layer-diode as set forth in claim 4, in which said electrical connection between said third electrode to said substrate is external of the substrate.

Claim 9

A planar four-layer-diode as set forth in claim 4 in which said third region has additional regions of the same impurity type and of high impurity concentration in the upper surface thereof, said insulating layer having a window therethrough below said third electrode through which said third electrode extends into contact with said additional region.