Self-protecting semiconductor device

Claim 1

In combination with a self-protected thyristor device including a p-type conductivity layer comprising the anode of said device, an n-type conductivity layer overlying said p-type conductivity layer and forming a first p-n junction therebetween, a second p-type conductivity layer overlying said n-type conductivity layer and forming a second p-n junction therebetween, a second n-type conductivity layer of annular configuration overlying a portion of said p-type conductivity layer and forming the main emitter of said device, a pilot thyristor region including a third n-type conductivity layer of annular configuration also overlying said second p-type conductivity layer and within the annular configuration of said main emitter, said third layer forming the pilot emitter of said device, and a gate region including an electrode contacting said second p-type region within the annular region of said pilot emitter, the improvement comprising: an etched region in said gate region, said etched region extending from the surface of said second p-type conductivity region for a sufficient depth in said second p-type region to reduce the breakdown voltage in said gate region below the breakdown voltage of said second p-n junction, said etched region providing a localized region of increased avalanche multiplication factor to insure that maximum current density at the onset of avalanche voltage breakdown occurs in the gate region, thereby causing said device to turn on in a controlled manner and prevent damage to said device.