Patent US4607178A successfully refreshed from Google Patents.
US4607178A
Expired / Lapsed
US
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Reset signal generating circuit
Assignee: Hitachi Ltd
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Filing: 1983-08-03
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Granted: 1986-08-19
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Expires: 2003-08-03
Abstract
Abstract A semiconductor integrated circuit receiving at its input pin the terminal voltage of a capacitor which is connected to a power source through a resistor so as to detect the level of the power voltage. The circuit is provided with a level shift circuit which shifts the incoming power voltage level by a predetermined value so that a reset signal is produced by detecting the output of the level shift circuit falling below the threshold level of a logic circuit.
Inventors
- 👤 Mamoru Sugie
- 👤 Takashi Toyooka
- 👤 Hirokazu Aoki
- 👤 Kazutoshi Yoshida
- 👤 Shinsaku Chiba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:44
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/223
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
339 words
A reset signal generating circuit for use in a semiconductor integrated circuit powered by a power source, comprising: delay means to be connected to said power source for producing a delayed voltage changing with a delay as the supply voltage of said power source changes, said delay means including a resistor, a capacitor connected to said power source through said resistor and a diode connected in parallel with said resistor, said delayed voltage being produced across said capacitor; a terminal connected to said capacitor for receiving said delayed voltage; level shift means, connected to said terminal, for shifting said delayed voltage by a predetermined voltage level including a first n-MOS transistor having a gate connected to said terminal and a drain to be connected to said power source, a first diode-connected n-MOS transistor having a drain connected to a source of said first n-MOS transistor, a second diode-connected n-MOS transistor having a drain connected to a source of said first diode-connected n-MOS transistor, and a first resistor connected between a source of said second diode-connected n-MOS transistor and ground, said shifted delayed voltage appearing at a first connection point connecting said first resistor and said source of said second diode-connected n-MOS transistor; and detecting means, connected to said level shift means, for detecting the level of said shifted delayed voltage to generate a reset signal when said shifted voltage is below a predetermined level, said reset signal being used to reset at least said integrated circuit, wherein said detecting means comprises: an inverter including a second n-MOS transistor having a gate connected to said first connection point and a source connected to ground and a second resistor of high resistance having one end connected to a drain of said second n-MOS transistor and the other end to be connected to said power source; and a Schmitt-trigger circuit having an input connected to a second connection point connecting said one end of said second resistor and said drain of said second n-MOS transistor and an output outputting said reset signal.
Claim 2
Dependent Claim
339 words
A reset signal generating circuit for use in a semiconductor integrated circuit powered by a power source, comprising: delay means to be connected to said power source for producing a delayed voltage changing with a delay as the supply voltage of said power source changes, said delay means including a resistor, a capacitor connected to said power source through said resistor and a diode connected in parallel with said resistor, said delayed voltage being produced across said capacitor; a terminal connected to said capacitor for receiving said delayed voltage; level shift means, connected to said terminal, for shifting said delayed voltage by a predetermined voltage level including a first n-MOS transistor having a gate connected to said terminal and a drain to be connected to said power source, a first diode-connected n-MOS transistor having a drain connected to a source of said first n-MOS transistor, a second diode-connected n-MOS transistor having a drain connected to a source of said first diode-connected n-MOS transistor, and a first resistor connected between a source of said second diode-connected n-MOS transistor and ground, said shifted delayed voltage appearing at a first connection point connecting said first resistor and said source of said second diode-connected n-MOS transistor; and detecting means, connected to said level shift means, for detecting the level of said shifted delayed voltage to generate a reset signal when said shifted voltage is below a predetermined level, said reset signal being used to reset at least said integrated circuit, wherein said detecting means comprises: an inverter including a second n-MOS transistor having a gate connected to said first connection point and a source connected to ground and a second resistor of high resistance having one end connected to a drain of said second n-MOS transistor and the other end to be connected to said power source; and a Schmitt-trigger circuit having an input connected to a second connection point connecting said one end of said second resistor and said drain of said second n-MOS transistor and an output outputting said reset signal.
Claim 3
Dependent Claim
100 words
A reset signal generating circuit according to claim 1, wherein said Schmitt-trigger circuit comprises: a first CMOS inverter connected between said power source and ground and having an input connected to said second connection point; a second CMOS inverter connected between said power source and ground and having an input connected to an output of said first CMOS inverter; and a third CMOS inverter having an input connected to an output of said second CMOS inverter and an output connected to said input of said second CMOS inverter, said reset signal appearing at said output of said second CMOS inverter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-18 | 1990-02-17 | 1990-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-18 | 1994-02-17 | 1994-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-18 | 1998-02-17 | 1998-08-19 | $7700.00 | Window Closed / Lapsed |