US4536667A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Reset pulse generator
Assignee: Sharp Corp
•
Filing: 1982-10-25
•
Granted: 1985-08-20
•
Expires: 2002-10-25
Abstract
Abstract A power supply circuit includes a regulator and a smoothing capacitor disposed at the input side of the regulator circuit for supplying power to a microcomputer included in a control system of an electric apparatus. The power supply circuit further includes a series circuit of a Zener diode and a resistor connected to the smoothing capacitor in a parallel fashion. When power supply is initiated, the node provided between the Zener diode and the resistor develops an initial reset pulse which is applied to a reset terminal of the microcomputer for initializing the microcomputer.
Inventors
- 👤 Sinichi Masuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:35
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
203 words
In a reset pulse generator circuit in a power supply circuit for developing an initial reset pulse to be applied to the reset terminal of a logic circuit, said power supply including a source of electrical power, a regulator circuit having an input side connected to said source of electrical power and an output side for supplying a regulated voltage to said logic circuit, the improvement comprising: a series circuit including a Zener diode and a resistor joined by a common node; said node being directly connected to the reset terminal of said logic circuit, one end of said resistor and one terminal of said Zener diode; the other end of said resistor being connected to one side of said source of electrical power; and the other terminal of said Zener diode being connected to the input side of said voltage regulator and the opposite side of said source of electrical power, said Zener diode being reverse biased to preclude the conduction thereof during steady state operation of said power supply circuit; and trigger means for forward biasing said Zener diode to generate said initial reset pulse at said node when said power supply suddenly goes fron an OFF to an ON state.
Claim 2
Dependent Claim
203 words
In a reset pulse generator circuit in a power supply circuit for developing an initial reset pulse to be applied to the reset terminal of a logic circuit, said power supply including a source of electrical power, a regulator circuit having an input side connected to said source of electrical power and an output side for supplying a regulated voltage to said logic circuit, the improvement comprising: a series circuit including a Zener diode and a resistor joined by a common node; said node being directly connected to the reset terminal of said logic circuit, one end of said resistor and one terminal of said Zener diode; the other end of said resistor being connected to one side of said source of electrical power; and the other terminal of said Zener diode being connected to the input side of said voltage regulator and the opposite side of said source of electrical power, said Zener diode being reverse biased to preclude the conduction thereof during steady state operation of said power supply circuit; and trigger means for forward biasing said Zener diode to generate said initial reset pulse at said node when said power supply suddenly goes fron an OFF to an ON state.
Claim 3
Dependent Claim
49 words
The reset pulse generator circuit of claim 1, wherein said trigger means comprises a smoothing capacitor connected in parallel with said source of electrical power and said Zener diode; whereby a sudden application of voltage across said smoothing capacitor generates a trigger voltage which forward biases said Zener diode.
Claim 4
Dependent Claim
15 words
The reset pulse generation circuit of claim 2, wherein said logic circuit comprises a microcomputer.
References Cited (Backward Citations)
US4296338A
Cited
US4300065A
Cited
US4405871A
Cited
US4429236A
Cited
US4367422A
Cited
US4367423A
Cited
US4433390A
Cited
US4438357A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-08-19 | 1989-02-18 | 1989-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-08-19 | 1993-02-18 | 1993-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-08-19 | 1997-02-18 | 1997-08-20 | $7700.00 | Window Closed / Lapsed |