US4520418A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Reset circuit
Assignee: Individual
•
Filing: 1983-04-25
•
Granted: 1985-05-28
•
Expires: 2003-04-25
Abstract
Abstract A reset circuit which monitors the voltage of the power supplied to a microprocessor unit, and produces a low resistance to ground at the reset terminal of the microprocessor whenever the supply voltage changes from a low value to a high value, or from a high value to a low value. It is based upon the combination of two RC circuits of different time constants, such that when the supply voltage is constant, no current flows in these circuits. A transistor is connected to the RC network such that it carries current only when there is a changing voltage of the power supply. If the voltage increases or decreases, a second transistor acting as an electronic switch grounds the reset terminal, and when the voltage becomes constant again, either at a high value or a low value, the switch opens and the reset voltage goes high.
Inventors
- 👤 Roger E. Susi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:08
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/223; H03K2017/226
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
248 words
A reset circuit for monitoring the power supply voltage of a microprocessor, and for disabling the action of said microprocessor for a selected time period, at the times of power supply voltage change, such as at times of power on and power off of the microprocessor, comprising: (a) a bridge network having four terminals, a first terminal A, a second terminal B, a third terminal C and a fourth terminal D, a first arm comprising a first diode D1 connected from terminal A to terminal B, a second arm comprising a first capacitor C2 connected from terminal B to terminal C, a third arm comprising a second capacitor C1 connected from terminal C to terminal D, and a fourth arm comprising a first resistor connected from terminal A to terminal D; (b) a power supply with voltage terminal V connected to terminal A and a ground terminal connected to terminal C; (c) the output terminals of said bridge are terminals B and D, with a load resistance R2 connected between them; (d) amplifier means connected across the output terminals B and D, said amplifier means having no direct connection to said power supply and receiving operating power only from said bridge when said bridge is unbalanced; (e) a reset terminal; and (f) an electronic switch means controlled by said amplifier means and being connected to said reset terminal, the switch means supplying a high voltage which serves as a reset voltage, when said amplifier means is turned off.
Claim 2
Dependent Claim
248 words
A reset circuit for monitoring the power supply voltage of a microprocessor, and for disabling the action of said microprocessor for a selected time period, at the times of power supply voltage change, such as at times of power on and power off of the microprocessor, comprising: (a) a bridge network having four terminals, a first terminal A, a second terminal B, a third terminal C and a fourth terminal D, a first arm comprising a first diode D1 connected from terminal A to terminal B, a second arm comprising a first capacitor C2 connected from terminal B to terminal C, a third arm comprising a second capacitor C1 connected from terminal C to terminal D, and a fourth arm comprising a first resistor connected from terminal A to terminal D; (b) a power supply with voltage terminal V connected to terminal A and a ground terminal connected to terminal C; (c) the output terminals of said bridge are terminals B and D, with a load resistance R2 connected between them; (d) amplifier means connected across the output terminals B and D, said amplifier means having no direct connection to said power supply and receiving operating power only from said bridge when said bridge is unbalanced; (e) a reset terminal; and (f) an electronic switch means controlled by said amplifier means and being connected to said reset terminal, the switch means supplying a high voltage which serves as a reset voltage, when said amplifier means is turned off.
Claim 3
Dependent Claim
58 words
The reset circuit as in claim 1 in which said amplifier means comprises first transistor means Q1 with its emitter connected to terminal B and its base to terminal D and its collector connected to ground through a resistor R3 and a capacitor C3 in parallel, and to electronic switch means connected between said reset terminal and ground.
Claim 4
Dependent Claim
26 words
The reset circuit as in claim 1 in which the voltage to be sensed for reset purposes is also the voltage that operates the reset circuit.
Claim 5
Dependent Claim
42 words
The reset circuit as in claim 2 in which said electronic switch means comprises a second transistor Q2 the gate of which is connected to the collector of Q1, its drain connected to ground, and its source connected to said reset terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-27 | 1988-11-26 | 1989-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-27 | 1992-11-26 | 1993-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-27 | 1996-11-26 | 1997-05-28 | $7700.00 | Window Closed / Lapsed |