US4605920A — Prescaling device and method

Claim 1

Independent Claim 196 words

A prescaling device for integrating an input signal and for generating an integrator output signal scaled with respect to the input signal, comprising: timer means for generating a timing signal at the end of each of a plurality of timing periods; integrator means responsive to the input signal for integrating the input signal to generate an integrator output signal proportional thereto, the integrator means including means for holding the integrator output signal in response to a hold signal; reference means for generating a reference signal; comparator means responsive to the integrator output signal and the reference signal for generating a signal when the integrator output signal is in a predetermined relationship with the reference signal; gating means for generating the hold signal in response to the comparator means signal and the timing signal whereby integration is halted at the end of one of the plurality of timing periods; and first counting means responsive to the timing signals for counting the number of timing periods before the integrator output signal was held to establish an integration timing range, such integration timing range providing an indication of a scaling factor to be applied to the integrator output signal.

Claim 2

Dependent Claim 196 words

A prescaling device for integrating an input signal and for generating an integrator output signal scaled with respect to the input signal, comprising: timer means for generating a timing signal at the end of each of a plurality of timing periods; integrator means responsive to the input signal for integrating the input signal to generate an integrator output signal proportional thereto, the integrator means including means for holding the integrator output signal in response to a hold signal; reference means for generating a reference signal; comparator means responsive to the integrator output signal and the reference signal for generating a signal when the integrator output signal is in a predetermined relationship with the reference signal; gating means for generating the hold signal in response to the comparator means signal and the timing signal whereby integration is halted at the end of one of the plurality of timing periods; and first counting means responsive to the timing signals for counting the number of timing periods before the integrator output signal was held to establish an integration timing range, such integration timing range providing an indication of a scaling factor to be applied to the integrator output signal.

Claim 3

Dependent Claim 32 words

A device as in claim 1 wherein the device further includes second counting means for counting the timing signals and for generating the hold signal after a predetermined number of timing periods.

Claim 4

Dependent Claim 80 words

A device as in claim 1 wherein the timer means further includes means for generating the timing signals such that each timing signal defines a timing range having a duration equal to the sum of the one or more timing periods which comprise the timing range and means for establishing the duration of each of the plurality of timing periods such that each timing range after a first timing range is twice as long as an immediately preceding timing range.

Claim 5

Dependent Claim 76 words

A device as in claim 1 wherein each timing signal defines a timing range having a duration equal to the sum of the previous timing periods which comprise the timing range and wherein the timer means includes means for establishing the duration of the plurality of timing periods such that the length of a timing range after a first timing range has a predetermined relationship with respect to the length of an immediately preceding timing range.

Claim 6

Dependent Claim 283 words

A prescaling device for integrating an input signal and for generating an integrator output signal scaled with respect to the input signal, comprising: integrator means responsive to the input signal for integrating the input signal to generate an integrator output signal proportional thereto, the integrator means including means for holding the integrator output signal in response to a hold signal; reference means for generating a reference signal; comparator means responsive to the integrator output signal and the reference signal for generating a signal when the integrator output signal is in a predetermined relationship with the reference signal; timer means for generating a timing signal at the end of each of a plurality of timing periods and timing ranges such that each timing range has a duration equal to the sum of the timing periods which comprise the timing range, the timer means including means for fixing the durations of the timing periods such that the duration of each timing range after a first timing range with respect to the duration of an immediately preceding timing range defines a predetermined ratio; gating means for generating the hold signal in response to the comparator means signal and the timing signal whereby integration can be halted at the end of one of the plurality of timing periods; first counting means responsive to the timing signals for counting the number of timing periods before the integrator output signal was held to establish an integration timing range, such integration timing range providing an indication of a scaling factor to be applied to the integrator output signal; and second counting means for counting the timing signals and for generating the hold signal after a predetermined number of timing periods.

Claim 7

Dependent Claim 283 words

A prescaling device for integrating an input signal and for generating an integrator output signal scaled with respect to the input signal, comprising: integrator means responsive to the input signal for integrating the input signal to generate an integrator output signal proportional thereto, the integrator means including means for holding the integrator output signal in response to a hold signal; reference means for generating a reference signal; comparator means responsive to the integrator output signal and the reference signal for generating a signal when the integrator output signal is in a predetermined relationship with the reference signal; timer means for generating a timing signal at the end of each of a plurality of timing periods and timing ranges such that each timing range has a duration equal to the sum of the timing periods which comprise the timing range, the timer means including means for fixing the durations of the timing periods such that the duration of each timing range after a first timing range with respect to the duration of an immediately preceding timing range defines a predetermined ratio; gating means for generating the hold signal in response to the comparator means signal and the timing signal whereby integration can be halted at the end of one of the plurality of timing periods; first counting means responsive to the timing signals for counting the number of timing periods before the integrator output signal was held to establish an integration timing range, such integration timing range providing an indication of a scaling factor to be applied to the integrator output signal; and second counting means for counting the timing signals and for generating the hold signal after a predetermined number of timing periods.

Claim 8

Dependent Claim 44 words

A device as in claim 5 wherein the gating means includes means for inhibiting the hold signal in response to an inhibit signal and the device further includes means for generating the inhibit signal until the predetermined number of timing periods have been generated.

Claim 9

Dependent Claim 73 words

A device as in claim 5 wherein the reference means includes means for generating the reference signal not greater than a predetermined signal level, the predetermined signal level defining a second predetermined ratio of a first signal range between first and second integrator output signal levels to a second signal range between the first integrator output signal level and the predetermined signal level, the second ratio being equal to the first predetermined ratio.

Claim 10

Dependent Claim 17 words

A device as in claim 7 wherein the first and second ratios are substantially equal to two.

Claim 11

Independent Claim 407 words

A system for converting an analog input signal into a scaled digital output comprising: integrator means responsive to the input signal for integrating the input signal to generate an integrator output signal proportional thereto, the integrator output signal varying within a first predetermined signal range between first and second signal levels, the integrator means further including means for holding the integrator output signal in response to a hold signal; reference means for generating a reference signal at a signal level not greater than a predetermined signal level, the predetermined signal level defining a second predetermined signal range between the integrator output signal first signal level and the predetermined signal level to thereby fix the reference signal level with respect to the first predetermined signal range; comparator means responsive to the integrator output signal and the reference signal for generating a signal when the integrator output signal is in a predetermined relationship with the reference signal; timer means for generating timing signals which define a plurality of timing periods and timing ranges such that each timing range has a duration equal to the sum of the timing periods which comprise the timing range, the timer means including means for establishing the duration of the plurality of timing periods such that a ratio of the length of a timing range after a first timing range to the length of an immediately preceding timing range is substantially equal to the ratio of the first predetermined signal range to the second predetermined signal range; gating means for generating the hold signal in response to concurrent reception of the comparator means signal and the timing signal whereby integration can be halted at the end of one of the plurality of timing periods; first counting means responsive to the timing signals for counting the number of timing periods before the integrator output signal was held for indicating the length of an integration timing range during which integration occurs; means responsive to the hold signal for generating a conversion command signal in response thereto; analog-to-digital converter means responsive to the integrator output signal and to the conversion command signal for converting the integrator output signal into a digital output; and processor means for determining a scaling factor equal to the ratio of the length of a calibration timing range to the length of the integration timing range and for multiplying the digital output by the scaling factor to thereby provide the scaled digital output.

Claim 12

Independent Claim 407 words

A system for converting an analog input signal into a scaled digital output comprising: integrator means responsive to the input signal for integrating the input signal to generate an integrator output signal proportional thereto, the integrator output signal varying within a first predetermined signal range between first and second signal levels, the integrator means further including means for holding the integrator output signal in response to a hold signal; reference means for generating a reference signal at a signal level not greater than a predetermined signal level, the predetermined signal level defining a second predetermined signal range between the integrator output signal first signal level and the predetermined signal level to thereby fix the reference signal level with respect to the first predetermined signal range; comparator means responsive to the integrator output signal and the reference signal for generating a signal when the integrator output signal is in a predetermined relationship with the reference signal; timer means for generating timing signals which define a plurality of timing periods and timing ranges such that each timing range has a duration equal to the sum of the timing periods which comprise the timing range, the timer means including means for establishing the duration of the plurality of timing periods such that a ratio of the length of a timing range after a first timing range to the length of an immediately preceding timing range is substantially equal to the ratio of the first predetermined signal range to the second predetermined signal range; gating means for generating the hold signal in response to concurrent reception of the comparator means signal and the timing signal whereby integration can be halted at the end of one of the plurality of timing periods; first counting means responsive to the timing signals for counting the number of timing periods before the integrator output signal was held for indicating the length of an integration timing range during which integration occurs; means responsive to the hold signal for generating a conversion command signal in response thereto; analog-to-digital converter means responsive to the integrator output signal and to the conversion command signal for converting the integrator output signal into a digital output; and processor means for determining a scaling factor equal to the ratio of the length of a calibration timing range to the length of the integration timing range and for multiplying the digital output by the scaling factor to thereby provide the scaled digital output.

Claim 13

Dependent Claim 32 words

A system as in claim 9 wherein the system further includes second counting means for counting the timing signals and for generating the hold signal after a predetermined number of timing periods.

Claim 14

Dependent Claim 154 words

A prescaling method for integrating an input signal and for generating an integrated output signal scaled with respect to the input signal, comprising the steps of: generating a timing signal at the end of each of a plurality of timing periods; integrating the input signal to generate an integrated output signal proportional thereto; generating a reference signal; comparing the integrated output signal and the reference signal and generating a comparison signal when the integrated output signal is in a predetermined relationship with the reference signal; holding the integrated output signal in respose to the comparison signal and the timing signal whereby integration is halted at the end of one of the plurality of timing periods; and counting the number of timing periods before the integrator output signal was held to establish an integration timing range, such integration timing range providing an indication of a scaling factor to be applied to the integrated output signal.

Claim 15

Dependent Claim 154 words

A prescaling method for integrating an input signal and for generating an integrated output signal scaled with respect to the input signal, comprising the steps of: generating a timing signal at the end of each of a plurality of timing periods; integrating the input signal to generate an integrated output signal proportional thereto; generating a reference signal; comparing the integrated output signal and the reference signal and generating a comparison signal when the integrated output signal is in a predetermined relationship with the reference signal; holding the integrated output signal in respose to the comparison signal and the timing signal whereby integration is halted at the end of one of the plurality of timing periods; and counting the number of timing periods before the integrator output signal was held to establish an integration timing range, such integration timing range providing an indication of a scaling factor to be applied to the integrated output signal.

Claim 16

Dependent Claim 36 words

A method as in claim 11 wherein the step of holding the integrated output includes the alternate step of counting the timing signals and holding the integrated output signal after a predetermined number of timing periods.

Claim 17

Dependent Claim 81 words

A method as in claim 11 wherein the step of generating the timing signal includes generating the timing signals such that each timing signal defines a timing range having a duration equal to the sum of the one or more timing periods which comprise the timing range and further includes establishing the duration of each of the plurality of timing periods such that each timing range after a first timing range is twice as long as an immediately preceding timing range.

Claim 18

Dependent Claim 84 words

A method as in claim 11 wherein the step of generating the timing signals includes generating the timing signals such that each timing signal defines a timing range having a duration equal to the sum of the timing periods which comprise the timing range and further includes establishing the duration of the plurality of timing periods such that the length of a timing range after a first timing range has a predetermined relationship with respect to the length of an immediately preceding timing range.

Claim 19

Dependent Claim 234 words

A prescaling method for integrating an input signal and for generating an integrated output signal scaled with respect to the input signal, comprising: integrating the input signal to generate an integrated output signal proportional thereto; generating a reference signal; comparing the integrated output signal and the reference signal and generating a comparison signal when the integrator output signal is in a predetermined relationship with the reference signal; generating timing signals which define a plurality of timing periods and timing ranges such that each timing range has a duration equal to the sum of the timing periods which comprise the timing range; fixing the durations of the timing periods such that the duration of each timing range after a first timing range with respect to the duration of an immediately preceding timing range defines a predetermined ratio; holding the integrated output signal in response to the comparison signal and the timing signal whereby integration is halted at the end of one of the plurality of timing periods, or counting the timing signals and holding the integrated output signal after a predetermined number of timing periods whereby integration is halted at a predetermined number of timing periods; and counting the number of timing periods before the integrator output signal was held to establish an integration timing range, such integration timing range providing an indication of a scaling factor to be applied to the integrated output signal.

Claim 20

Dependent Claim 234 words

A prescaling method for integrating an input signal and for generating an integrated output signal scaled with respect to the input signal, comprising: integrating the input signal to generate an integrated output signal proportional thereto; generating a reference signal; comparing the integrated output signal and the reference signal and generating a comparison signal when the integrator output signal is in a predetermined relationship with the reference signal; generating timing signals which define a plurality of timing periods and timing ranges such that each timing range has a duration equal to the sum of the timing periods which comprise the timing range; fixing the durations of the timing periods such that the duration of each timing range after a first timing range with respect to the duration of an immediately preceding timing range defines a predetermined ratio; holding the integrated output signal in response to the comparison signal and the timing signal whereby integration is halted at the end of one of the plurality of timing periods, or counting the timing signals and holding the integrated output signal after a predetermined number of timing periods whereby integration is halted at a predetermined number of timing periods; and counting the number of timing periods before the integrator output signal was held to establish an integration timing range, such integration timing range providing an indication of a scaling factor to be applied to the integrated output signal.

Claim 21

Dependent Claim 77 words

A method as in claim 15 wherein the step of generating the reference signal further includes generating the reference signal not greater than a predetermined signal level, the predetermined signal level defining a second predetermined ratio of a first signal range between first and second integrator output signal levels to a second signal range between the first integrator output signal level and the predetermined signal level, the second ratio being equal to the first named predetermined ratio.

Claim 22

Dependent Claim 19 words

A method as in claim 16 further including fixing the first and second predetermined ratios substantially equal to two.

Claim 23

Dependent Claim 35 words

A method as in claim 15 wherein the step of holding the integrated output signal further includes inhibiting the holding of the integrated output signal until a predetermined number of timing periods have been generated.

Claim 24

Independent Claim 304 words

A method for converting an analog input signal into a scaled digital output comprising the steps of: integrating the input signal to generate an integrated output signal proportional therto, the integrated output signal varying within a first predetermined signal range between first and second signal levels; generating a reference signal at a signal level not greater than a predetermined signal level, the predetermined signal level defining a second predetermined signal range between the integrated output signal first signal level and the predetermined signal level; comparing the integrated output signal and the reference signal and generating a comparison signal when the integrated output signal is in a predetermined relationshp with the reference signal; generating timing signals which define a plurality of timing periods and timing ranges such that each timing range has a duration equal to the sum of the timing periods which comprise the timing range; establishing the duration of the plurality of timing periods such that a ratio of the length of a timing range after a first timing range to the length of an immediately preceding timing range is substantially equal to the ratio of the first predetermined signal range to the second predetermined signal range; holding the integrated output signal in response to the comparison signal and the timing signal whereby integration is halted at the end of one of the plurality of timing periods; counting the number of timing periods before the integrator output signal was held to establish an integration timing range; converting the integrated output signal into a digital output at the end of the integration timing range; determining a scaling factor equal to the ratio of the length of a calibration timing range to the length of the integration timing range; and multiplying the digital output by the scaling factor to thereby provide the scaled digital output.

Claim 25

Independent Claim 304 words

A method for converting an analog input signal into a scaled digital output comprising the steps of: integrating the input signal to generate an integrated output signal proportional therto, the integrated output signal varying within a first predetermined signal range between first and second signal levels; generating a reference signal at a signal level not greater than a predetermined signal level, the predetermined signal level defining a second predetermined signal range between the integrated output signal first signal level and the predetermined signal level; comparing the integrated output signal and the reference signal and generating a comparison signal when the integrated output signal is in a predetermined relationshp with the reference signal; generating timing signals which define a plurality of timing periods and timing ranges such that each timing range has a duration equal to the sum of the timing periods which comprise the timing range; establishing the duration of the plurality of timing periods such that a ratio of the length of a timing range after a first timing range to the length of an immediately preceding timing range is substantially equal to the ratio of the first predetermined signal range to the second predetermined signal range; holding the integrated output signal in response to the comparison signal and the timing signal whereby integration is halted at the end of one of the plurality of timing periods; counting the number of timing periods before the integrator output signal was held to establish an integration timing range; converting the integrated output signal into a digital output at the end of the integration timing range; determining a scaling factor equal to the ratio of the length of a calibration timing range to the length of the integration timing range; and multiplying the digital output by the scaling factor to thereby provide the scaled digital output.

Claim 26

Dependent Claim 47 words

A method as in claim 19 wherein the method includes the additional step of counting the timing signal and holding the integrated output after a predetermined number of timing periods whereby integration can be halted at a maximum timing range after the predetermined number of timing periods.

Claim 27

Dependent Claim 282 words

A switching device for an integrator wherein the integrator includes an input terminal, an output terminal, and an integrating element connected between the input and output terminals, the switching device comprising: a first solid-state switch having a first switched terminal connected to the integrator input terminal, a second switched terminal adapted to receive an input signal, and a control terminal adapted to receive a first control signal for controlling conduction between the first and second switched terminals; a second solid-state switch having a first switched terminal connected to the integrator input terminal, a second switched terminal and a control terminal adapted to receive a second control signal for controlling conduction between the first and second switched terminals; a third solid-state switch having a first switched terminal connected to the integrator output terminal, a second switched terminal connected to the second switched terminal of the second solid-state switch, and a control terminal adapted to receive a control signal for controlling conduction between the first and second switched terminals; and a switching controller responsive to integrate, hold and reset signals and including means for generating the first, second and third control signals such that the first solid-state switch conducts and the second solid-state switch does not conduct in response to the integrate signal, the first and third solid-state switches do not conduct and the second solid-state switch does conduct in response to the hold signal, and the first solid-state switch does not conduct while the second and third solid-state switches conduct in response to the reset signal, the first and second solid-state switches being operated in a reciprocal fashion to reduce the influence of change injection from such switches into the integrator input terminal.

Claim 28

Dependent Claim 282 words

A switching device for an integrator wherein the integrator includes an input terminal, an output terminal, and an integrating element connected between the input and output terminals, the switching device comprising: a first solid-state switch having a first switched terminal connected to the integrator input terminal, a second switched terminal adapted to receive an input signal, and a control terminal adapted to receive a first control signal for controlling conduction between the first and second switched terminals; a second solid-state switch having a first switched terminal connected to the integrator input terminal, a second switched terminal and a control terminal adapted to receive a second control signal for controlling conduction between the first and second switched terminals; a third solid-state switch having a first switched terminal connected to the integrator output terminal, a second switched terminal connected to the second switched terminal of the second solid-state switch, and a control terminal adapted to receive a control signal for controlling conduction between the first and second switched terminals; and a switching controller responsive to integrate, hold and reset signals and including means for generating the first, second and third control signals such that the first solid-state switch conducts and the second solid-state switch does not conduct in response to the integrate signal, the first and third solid-state switches do not conduct and the second solid-state switch does conduct in response to the hold signal, and the first solid-state switch does not conduct while the second and third solid-state switches conduct in response to the reset signal, the first and second solid-state switches being operated in a reciprocal fashion to reduce the influence of change injection from such switches into the integrator input terminal.

Claim 29

Dependent Claim 20 words

A switching device as in claim 21 wherein the first and second solid-state switches are formed on a single substrate.

Claim 30

Dependent Claim 41 words

A switching device as in claim 22 wherein the switching controller includes means for opening the third solid-state switch after the second solid-state switch is opened to further reduce charge injection by the third solid-state switch into the integrator input terminal.

Claim 31

Dependent Claim 311 words

A switching device for an integrator wherein the integrator includes an input terminal, an output terminal, and an integrating element connected between the input and output terminals, the switching device comprising: first, second and third solid-state switches formed on a single substrate; the first solid-state switch having a first switched terminal connected to the integrator input terminal, a second switched terminal adapted to receive an input signal, and a control terminal adapted to receive a first control signal for controlling conduction between the first and second switched terminals; the second solid-state switch having a first switched terminal connected to the integrator input terminal, a second switched terminal and a control terminal adapted to receive a second control signal for controlling conduction between the first and second switched terminals; the third solid-state switch having a first switched terminal connected to the integrator output terminal, a second switched terminal connected to the second switched terminal of the second solid-state switch, and a control terminal adapted to receive a control signal for controlling conduction between the first and second switched terminals; and a switching controller responsive to integrate, hold and reset signals and including means for generating the first, second and third control signals such that the first solid-state switch conducts and the second solid-state switch does not conduct in response to the integrate signal, the first and third solid-state switches do not conduct and the second solid-state switch does conduct in response to the hold signal, and the first solid-state switch does not conduct while the second and third solid-state switches conduct in response to the reset signal, the switching controller including means for opening the third solid-state switch after the second solid-state switch is opened, the first and second solid-state switches being operated in a reciprocal fashion to reduce the influence of charge injection from such switches into the integrator input terminal.

Claim 32

Dependent Claim 311 words

A switching device for an integrator wherein the integrator includes an input terminal, an output terminal, and an integrating element connected between the input and output terminals, the switching device comprising: first, second and third solid-state switches formed on a single substrate; the first solid-state switch having a first switched terminal connected to the integrator input terminal, a second switched terminal adapted to receive an input signal, and a control terminal adapted to receive a first control signal for controlling conduction between the first and second switched terminals; the second solid-state switch having a first switched terminal connected to the integrator input terminal, a second switched terminal and a control terminal adapted to receive a second control signal for controlling conduction between the first and second switched terminals; the third solid-state switch having a first switched terminal connected to the integrator output terminal, a second switched terminal connected to the second switched terminal of the second solid-state switch, and a control terminal adapted to receive a control signal for controlling conduction between the first and second switched terminals; and a switching controller responsive to integrate, hold and reset signals and including means for generating the first, second and third control signals such that the first solid-state switch conducts and the second solid-state switch does not conduct in response to the integrate signal, the first and third solid-state switches do not conduct and the second solid-state switch does conduct in response to the hold signal, and the first solid-state switch does not conduct while the second and third solid-state switches conduct in response to the reset signal, the switching controller including means for opening the third solid-state switch after the second solid-state switch is opened, the first and second solid-state switches being operated in a reciprocal fashion to reduce the influence of charge injection from such switches into the integrator input terminal.

Claim 33

Independent Claim 321 words

A method for controlling a switching device for an integrator wherein the integrator includes an input terminal, an output terminal, and an integrating element connected between the input and output terminals, wherein the switching device includes: a first solid-state switch having a first switched terminal connected to the integrator input terminal, a second switched terminal adapted to receive an input signal, and a control terminal adapted to receive a first control signal for controlling conduction between the first and second switched terminals; a second solid-state switch having a first switched terminal connected to the integrator input terminal, a second switched terminal and a control terminal adapted to receive a second control signal for controlling conduction between the first and second switched terminals; a third solid-state switch having a first switched terminal connected to the integrator output terminal, a second switched terminal connected to the second switched terminal of the second solid-state switch, and a control terminal adapted to receive a control signal for controlling conduction between the first and second switched terminals; and a switching controller responsive to integrate, hold and reset signals and including means for generating the first, second and third control signals, the method including the steps of: generating the first, second and third control signals such that the first solid-state switch conducts and the second solid-state switch does not conduct in response to the integrate signal; generating the first, second and third control signals such that the first and third solid-state switches do not conduct and the second solid-state switch does conduct in response to the hold signal; and generating the first, second and third control signals such that the first solid-state switch does not conduct while the second and third solid-state switches conduct in response to the reset signal, the first and second solid-state switches being operated in a reciprocal fashion to reduce the influence of change injection from such switches into the integrator input terminal.

Claim 34

Independent Claim 321 words

A method for controlling a switching device for an integrator wherein the integrator includes an input terminal, an output terminal, and an integrating element connected between the input and output terminals, wherein the switching device includes: a first solid-state switch having a first switched terminal connected to the integrator input terminal, a second switched terminal adapted to receive an input signal, and a control terminal adapted to receive a first control signal for controlling conduction between the first and second switched terminals; a second solid-state switch having a first switched terminal connected to the integrator input terminal, a second switched terminal and a control terminal adapted to receive a second control signal for controlling conduction between the first and second switched terminals; a third solid-state switch having a first switched terminal connected to the integrator output terminal, a second switched terminal connected to the second switched terminal of the second solid-state switch, and a control terminal adapted to receive a control signal for controlling conduction between the first and second switched terminals; and a switching controller responsive to integrate, hold and reset signals and including means for generating the first, second and third control signals, the method including the steps of: generating the first, second and third control signals such that the first solid-state switch conducts and the second solid-state switch does not conduct in response to the integrate signal; generating the first, second and third control signals such that the first and third solid-state switches do not conduct and the second solid-state switch does conduct in response to the hold signal; and generating the first, second and third control signals such that the first solid-state switch does not conduct while the second and third solid-state switches conduct in response to the reset signal, the first and second solid-state switches being operated in a reciprocal fashion to reduce the influence of change injection from such switches into the integrator input terminal.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1989-08-11	1990-02-10	1990-08-12	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1993-08-11	1994-02-10	1994-08-12	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1997-08-11	1998-02-10	1998-08-12	$7700.00	Window Closed / Lapsed

Prescaling device and method

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