Analog-to-digital converter

Claim 3

The improved method of claim 1 including the step of: A. registering the number of analog signals to be converted in succession in an additional counter (ZZ), and B. determining the amount of said additional voltage to be added to said storage means in accordance with the number of said analog signals which are registered by said additional counter.

Claim 4

The improved method of claim 2 including the step of automatically resetting said additional counter (ZZ) after it reaches a preset number.

Claim 5

In apparatus for converting analog values to digital values comprising, in combination: A. means for storing an electric charge, B. means for delivering an electric charge to said storage means whose quantity corresponds to an analog signal to be converted, C. means for measuring the time for change in charge thereafter occurring in said electric charge storage means during a first time period at a rate higher than in a second timing period and at a higher evaluation, D. means for measuring the time for remaining change in charge during a second time period at a lower rate and a corresponding lower evaluation during the second period, the improvement wherein means for evaluating the said remaining change in charge at a lower evaluation during said second time period comprises means for supplying an additional voltage charge (S2) to said storage means (SP) in an amount corresponding to the number of analog values to be converted in succession.

Claim 6

In apparatus for converting analog values to digital values comprising, in combination: A. means for storing an electric charge, B. means for delivering an electric charge to said storage means whose quantity corresponds to an analog signal to be converted, C. means for measuring the time for change in charge thereafter occurring in said electric charge storage means during a first time period at a rate higher than in a second timing period and at a higher evaluation, D. means for measuring the time for remaining change in charge during a second time period at a lower rate and a corresponding lower evaluation during the second period, the improvement wherein means for evaluating the said remaining change in charge at a lower evaluation during said second time period comprises means for supplying an additional voltage charge (S2) to said storage means (SP) in an amount corresponding to the number of analog values to be converted in succession.

Claim 7

The improVement of claim 4 wherein said means for measuring time include first counter means for counting pulses, and means for supplying cyclical pulses to said counter means during said first and second time periods and also at the same time as said additional charge is supplied to said storage means.

Claim 8

The improvement of claim 5 including additional counter means for counting the number of analog signals to be converted in succession and means for comparing the count in said additional counter means with the count in said first-mentioned counter means and for controlling the amount of said additional electric charge to be added to said storage means and the number of said cyclical pulses supplied to said counter at the same time as said additional charge is supplied.

Claim 9

The improvement of claim 6 including: A. a first triggering means (F1) for blocking said storage means (SP) from further storage of said analog values after a discharge by a first analog signal, B. a first current source (S1) for supplying a charging voltage to said storage means (SP) to thereby give a higher evaluation to pulses produced while said current source is so connected, C. a second triggering means (F2) connected to said first triggering means to be set thereby and connected to said timing pulses to be actuated thereby for connecting said first current source to said storage means and for opening a first input (F) of said first counter means (Z) to the receipt of said cyclical pulses, D. means for delivering a signal representing an intermediate level of charge storage at said storage means, E. a third triggering means connected to be set by said signal from said storage means and triggered by said counting pulses to reset said triggering means and for opening a second input (R) of said first counter means (Z) to receipt of timing signals, F. a fourth triggering means arranged to be set by said third triggering means and triggered by said timing pulses, G. comparator circuit means for comparing the contents of said first counter (Z) and said second counter (ZZ), H. reversing switch means (WS) actuated by said comparator means to deliver the output of said first triggering means to said second triggering means after a delay when the contents of said second counter means (ZZ) is equal to or smaller than said first counter (Z) and for delivering the output of said first triggering means to a second output when the contents of said second counter (ZZ) is greater than said first counter (Z), I. an OR-gate (G7) having one of its inputs connected to said second output of said reversing switch means and its other input connected to said fourth triggering means, J. a second current source controlled by said OR-gate (G7) to deliver a charging current to said storage means (SP) to thereby cause pulses counted during the discharge of said storage means while said second current source is connected thereto to have a lower valuation than pulses delivered when said first current source is connected thereto, and K. and AND-gate (G3) having one input connected to said OR-gate (G7), its other input to receive said timing pulses, and its output to said second input (R) of said first counter (Z).