US3774018A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-range signal integrator which changes range only at specific times
Assignee: PE Manufacturing GmbH
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Filing: 1971-12-08
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Granted: 1973-11-20
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Expires: 1991-12-08
Abstract
Abstract A known multirange integrator includes a multistep voltage divider (e.g., 1, 1/10, 1/100) for the input signal, an analogto-digital converter for generating counting pulses at a frequency proportional to the (divided) input voltage, a final counter for these pulses, and a multistep switching arrangement for effectively multiplying the ''''weighting'''' of the pulses by a factor (e.g., 1, 10, 100) to counteract the effect of the input voltage divider (as by supplying the pulses to different stages of a, say, decade counter). The analog-to-digital converter may be a resettable integrator which supplies a counting pulse when its output reaches a preset value, the integrator being simultaneously reset by supplying a reset signal (of standardized voltage and time) to its input. The improvement insures that range switching (of the input divider and output ''''weighting'''' switching arrangement) does not occur during the production of a counting pulse by the resettable integrator, which would cause the input signal to be (at least in part) integrated as divided by one factor and the resulting pulse later counted at a different weighting factor. In particular, although the range chosen is dependent on the amplitude of the input signal, actual switching to a new range occurs only when a counting pulse is generated, thereby occurring during the integration reset interval. This switching may be caused by flip-flops setting each range, which flip-flops are enabled by a logic circuit and limit switches reading the input level, but which actually change state only upon occurrence of a counting pulse.
Inventors
- 👤 E Spreitzhofer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:53
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
290 words
In a multirange input signal integrator of the type comprising in series: a switchable multistep input voltage divider, an integrating stage, means supplying a counting pulse whenever a preset value of the output of the integrating stage is reached and for simultaneously supplying a reset signal to return the integrating stage to its nominal zero level, said integrating stage and reset signal supplying means therefore acting as voltage-to-frequency converter to generate counting pulses at a frequency proportional to the amplitude of the input voltage after division by the voltage divider, a pulse counter having a multistep count-weighting switching means so as to count said pulses as effectively multiplied by a factor equal to the division factor of said multistep input voltage divider, and means for causing ganged switching of both said multistep input voltage divider and said multistep count-weighting switching means when different ranges of the input voltage to be measured are reached, without effecting the overall proportionality between the undivided input voltage and the final count of the counter, the improvement comprising: said means for causing said ganged switching comprises, in addition to means responsive to the value of said input voltage, (K1, K2) initialing means (FF1, FF2, FF3) responsive to said counting pulse, said ganged switching causing means being of such construction that said initiating means actually causes switching of said multistep input voltage divider and said multistep countweighting switching means only at the time of occurrence of said counting pulse, whereby the range changing always occurs when said integrating stage is reset, thereby avoiding error which would be caused by partial integration of an input signal at one setting of the voltage divider and count-weighting switching means and countweighting at a different setting of said switching means.
Claim 2
Dependent Claim
290 words
In a multirange input signal integrator of the type comprising in series: a switchable multistep input voltage divider, an integrating stage, means supplying a counting pulse whenever a preset value of the output of the integrating stage is reached and for simultaneously supplying a reset signal to return the integrating stage to its nominal zero level, said integrating stage and reset signal supplying means therefore acting as voltage-to-frequency converter to generate counting pulses at a frequency proportional to the amplitude of the input voltage after division by the voltage divider, a pulse counter having a multistep count-weighting switching means so as to count said pulses as effectively multiplied by a factor equal to the division factor of said multistep input voltage divider, and means for causing ganged switching of both said multistep input voltage divider and said multistep count-weighting switching means when different ranges of the input voltage to be measured are reached, without effecting the overall proportionality between the undivided input voltage and the final count of the counter, the improvement comprising: said means for causing said ganged switching comprises, in addition to means responsive to the value of said input voltage, (K1, K2) initialing means (FF1, FF2, FF3) responsive to said counting pulse, said ganged switching causing means being of such construction that said initiating means actually causes switching of said multistep input voltage divider and said multistep countweighting switching means only at the time of occurrence of said counting pulse, whereby the range changing always occurs when said integrating stage is reset, thereby avoiding error which would be caused by partial integration of an input signal at one setting of the voltage divider and count-weighting switching means and countweighting at a different setting of said switching means.
Claim 3
Dependent Claim
126 words
In a multirange input signal integrator according to claim 1, in which said means for causing said ganged switching comprises: limit value switches (K1, K2) responsive to the level of the input signal; flip-flops (FF1, FF2, FF3) for controlling the various steps of both said multistep input voltage divider and said multistep count-weighting switching means; logic circuitry (I1, I2, G1, G2, G3) for connecting the outputs of said limit value switches to the enabling inputs of said flip-flops; and means (10) supplying said counting pulses to the actuating inputs of said flip-flops, whereby said flip-flops actually change their state only upon occurrence of a counting pulse, although they are generally controlled by the input signal level as determined by said limit value switches and logic circuitry.
Claim 4
Dependent Claim
299 words
In a multirange input signal integrator according to claim 2, in which: said limit value switches comprise a first limit switch (K1) which changes its state whenever the input signal level crosses an intermediate value between a first and second measuring range, and a second limit switch (K2) which changes its state whenever the input signal level crosses a higher value between the second and a third measuring range; said logic circuitry comprises: first and second inverters (I1, I2) having their inputs connected to the output of, respectively, said first and second limit switches; first, second and third AND gates (G1, G2, G3), the two inputs of the first (G1) of which receives the outputs of each of said inverters, the two inputs of the second (G2) of which receives the output of said first limit switch and the output of said second inverter, and the two inputs of the third (G3) of which receives the output of each of said limit switches, so that the output of each AND gate assumes a particular stage when said input signal is in a corresponding one of said first, second or third measuring range; the outputs of each of said AND gates being connected to the enabling input of a corresponding one of said flip-flops, whereby when the input signal level crosses from one measuring range to another, these two flip-flops corresponding to the two involved ranges will each change their states upon the occurrence of the next succeeding counting pulse so as to change the integration range by switching the multistep voltage divider and multistep count-weighting switching means from the step corresponding to the previous input signal level range to the present one, without risk of even partial integration at one range setting and pulse counting at a different one.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-11-19 | 1977-05-21 | 1977-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-11-19 | 1981-05-21 | 1981-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-11-19 | 1985-05-21 | 1985-11-20 | $7700.00 | Window Closed / Lapsed |