US4404545A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog-to-digital converter of the dual slope type
Assignee: Sharp Corp
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Filing: 1981-04-28
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Granted: 1983-09-13
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Expires: 2001-04-28
Abstract
Abstract Errors in determining a measured voltage are mathematically canceled in an analog-to-digital converter circuit useful for dual slope type using positive and negative values of a reference voltage. The errors are due to the off-set voltages inherent to operational amplifiers employed for an integrator and a comparator included within the analog-to-digital converter circuit. A counter circuit is provided for storing time information related to first and second dual slopes. A mathematical calculation is conducted with the aid of all the time information of the first and second dual slopes, whereby the measured voltage can be determined with eliminating the influence by the off-set voltage.
Inventors
- 👤 Tousaku Nakanishi
- 👤 Hiroshi Tsuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:28
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/08; H03M1/12; H03M1/50; H03M1/52
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
351 words
A semiconductor electronic circuit for determining an unknown voltage value while compensating for an offset error voltage present in said circuitry comprising: a first switched input means for selectively receiving a first reference voltage; a second switched input means for selectively receiving a second reference voltage equal to said first reference voltage but reversed in polarity; a third switched input means for selectively receiving an unknown voltage value; an integrator including a differential amplifier and a feedback capacitor, said integrator being connected to said first, second, and third switched input means and having an output; said first switched input means selectively receiving and providing said first reference voltage to said integrator during a first predetermined time period to produce a first integrated voltage value at the output of said integrator, said first predetermined time period beginning when said integrator produces an output greater than zero; said second switched input means selectively receiving and providing said second reference voltage to said integrator after said first predetermined timed period is completed and until the output of said integrator equals zero; means for measuring the duration of the integration of the input applied by said second switched input means after said first predetermined time period to form a first measured time period; said third switched input means selectively receiving and providing said unknown voltage to said integrator during a second predetermined time period to produce a second integrated voltage value at the output of said integrator, said second predetermined time period beginning when said integrator produces an output greater than zero; said second switched input means selectively receiving and applying said second reference voltage to said integrator after said second predetermined time period is completed and until output of said integrator is zero; means for measuring the duration of the integration of the input applied by said second switched input means after said second predetermined time period to form a second measured time period; and means for determining the value of said unknown voltage using said first and second predetermined time periods, said first and second measured time periods and said first reference voltage.
Claim 2
Dependent Claim
351 words
A semiconductor electronic circuit for determining an unknown voltage value while compensating for an offset error voltage present in said circuitry comprising: a first switched input means for selectively receiving a first reference voltage; a second switched input means for selectively receiving a second reference voltage equal to said first reference voltage but reversed in polarity; a third switched input means for selectively receiving an unknown voltage value; an integrator including a differential amplifier and a feedback capacitor, said integrator being connected to said first, second, and third switched input means and having an output; said first switched input means selectively receiving and providing said first reference voltage to said integrator during a first predetermined time period to produce a first integrated voltage value at the output of said integrator, said first predetermined time period beginning when said integrator produces an output greater than zero; said second switched input means selectively receiving and providing said second reference voltage to said integrator after said first predetermined timed period is completed and until the output of said integrator equals zero; means for measuring the duration of the integration of the input applied by said second switched input means after said first predetermined time period to form a first measured time period; said third switched input means selectively receiving and providing said unknown voltage to said integrator during a second predetermined time period to produce a second integrated voltage value at the output of said integrator, said second predetermined time period beginning when said integrator produces an output greater than zero; said second switched input means selectively receiving and applying said second reference voltage to said integrator after said second predetermined time period is completed and until output of said integrator is zero; means for measuring the duration of the integration of the input applied by said second switched input means after said second predetermined time period to form a second measured time period; and means for determining the value of said unknown voltage using said first and second predetermined time periods, said first and second measured time periods and said first reference voltage.
Claim 3
Dependent Claim
14 words
The circuit of claim 1, wherein said means for determining includes a digital computer.
Claim 4
Dependent Claim
17 words
The circuit of claim 1, wherein said circuit for determining functions as an analog to digital converter.
Claim 5
Dependent Claim
62 words
The circuit of claim 2, wherein the value of said unknown voltage is solved by said means for determining using the equation: ##EQU10## V r is said first reference voltage; t 1 is said first predetermined time period; t 2 is said first measured time period; t 3 is said second predetermined time period; t 4 is said second measured time period.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-12 | 1987-03-14 | 1987-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-12 | 1991-03-14 | 1991-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-12 | 1995-03-14 | 1995-09-13 | $7700.00 | Window Closed / Lapsed |