Patent US4601760A successfully refreshed from Google Patents.
US4601760A
Expired / Lapsed
US
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Ion-implanted process for forming IC wafer with buried-reference diode and IC structure made with such process
Assignee: Analog Devices Inc
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Filing: 1985-09-16
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Granted: 1986-07-22
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Expires: 2005-09-16
Abstract
Abstract A new process making it possible to produce stable buried Zener diodes in large-sized wafers where slow ramping of diffusion temperatures is required to avoid crystal damage and other adverse effects. The process includes an initial deep ion implantation of p type dopant (boron). A second ion implantation of n type dopant (arsenic) is made over the p type implantation. Both implantations are driven in to the required degree. An additional p type dopant diffusion is made coincident with the base formation by ion implantation to establish connection to the original deep p-doped region, and an additional n type dopant diffusion is made coincident with the emitter formation to establish connection with the n type dopant implantation.
Inventors
- 👤 Steven M. Hemmah
- 👤 Richard S. Payne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:22
CPC Classifications
H; H10; H10D; H10D8/00; H10D8/20; H10D8/25; H10P; H10P30/00; H10P30/20; Y; Y10; Y10S; Y10S438/00; Y10S438/983
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
124 words
The method of making an IC wafer with a buried reference diode comprising the steps of: implanting p-type ions in said wafer to form a p-type first region extending a substantial distance into the wafer; implanting n-type ions in said wafer to form an n-type second region directly over said p-type region and forming therewith an all-implanted sub-surface junction suitable for stable breakdown; providing means for establishing electrical connection to said n-type second region; and forming with p-type dopant a third region joining said p-type first region below the surface of said wafer and extending out laterally beyond said p-type first region to the surface of said wafer to provide for making electrical connection to the p-type first region side of said sub-surface junction.
Claim 2
Independent Claim
124 words
The method of making an IC wafer with a buried reference diode comprising the steps of: implanting p-type ions in said wafer to form a p-type first region extending a substantial distance into the wafer; implanting n-type ions in said wafer to form an n-type second region directly over said p-type region and forming therewith an all-implanted sub-surface junction suitable for stable breakdown; providing means for establishing electrical connection to said n-type second region; and forming with p-type dopant a third region joining said p-type first region below the surface of said wafer and extending out laterally beyond said p-type first region to the surface of said wafer to provide for making electrical connection to the p-type first region side of said sub-surface junction.
Claim 3
Dependent Claim
29 words
The method of claim 1, wherein said p-type ions in said sub-surface junction have a higher concentration than said p-type dopant in any surface junction with said n-type ions.
Claim 4
Dependent Claim
21 words
The method of claim 1, wherein said n-type ions make an n++ region and said p-type ions make a p++ region.
Claim 5
Dependent Claim
11 words
The method of claim 1, wherein said n-type ions are arsenic.
Claim 6
Dependent Claim
21 words
The method of claim 1, wherein said p-type dopant is driven into said third region of the wafer by ion implantation.
Claim 7
Dependent Claim
24 words
The method of claim 1, wherein said n-type ions and said p-type ions are implanted through a common opening formed by a single mask.
Claim 8
Dependent Claim
29 words
The method of claim 1, wherein said p-type third region is formed to extend out laterally beyond said n-type second region to reach to the surface of said wafer.
Claim 9
Dependent Claim
34 words
The method of claim 1, wherein said n-type ions extend laterally beyond said p-type ions in any surface region of said wafer in a vertical plane containing said p-type dopant and said n-type ions.
Claim 10
Dependent Claim
15 words
The method of claim 3, wherein said sub-surface junction is parallel to the wafer surface.
Claim 11
Dependent Claim
11 words
The method of claim 4, wherein said p-type ions are boron.
Claim 12
Dependent Claim
41 words
The method of claim 6, wherein the opening defined for the n-type ion implantation is slightly enlarged relative to the opening size during the p-type ion implantation, to assure that the n-type ions extend laterally beyond the region of p-type ions.
Claim 13
Dependent Claim
18 words
The method of claim 9, wherein said n++ ions extend laterally beyond said p++ ions in all directions.
Claim 14
Dependent Claim
95 words
The method of claim 11, wherein to define said opening for the ion implantation steps, the following steps are carried out: depositing oxide on the wafer; depositing nitride on the oxide; etching the nitride; etching said oxide with the etched nitride serving as the mask, so as to form said opening; implanting said p-type ions through said opening; further etching said oxide to form an undercut region beneath said nitride around the periphery of said opening; and removing said nitride layer to allow the n-type ion implantation to be made through the resulting enlarged opening.
Claim 15
Independent Claim
92 words
The method of making an IC wafer with a buried reference diode comprising the steps of: implanting p-type ions in said wafer to form a p-type first region extending a substantial distance into the wafer; implanting n-type ions in said wafer to form an n-type second region over said p-type region and forming therewith an all-implanted sub-surface junction suitable for stable breakdown; said junction extending at least substantially parallel to the surface of the wafer; and providing means for establishing electrical connection to said p-type first region and said n-type second region.
Claim 16
Independent Claim
92 words
The method of making an IC wafer with a buried reference diode comprising the steps of: implanting p-type ions in said wafer to form a p-type first region extending a substantial distance into the wafer; implanting n-type ions in said wafer to form an n-type second region over said p-type region and forming therewith an all-implanted sub-surface junction suitable for stable breakdown; said junction extending at least substantially parallel to the surface of the wafer; and providing means for establishing electrical connection to said p-type first region and said n-type second region.
Claim 17
Dependent Claim
61 words
The method of claim 14 including the step of establishing a third region with p-type dopant, said third region joining said p-type first region below the surface of said wafer and extending out laterally beyond said p-type first region to the surface of said wafer to provide for making electrical connection to the p-type first region side of said sub-surface junction.
Claim 18
Dependent Claim
41 words
The method of claim 15, wherein said connection to said n region is established by placing n-type second dopant in a surface region which overlaps said implanted n-type ions and is separated from the p-type dopant in said laterally extending region.
Claim 19
Dependent Claim
27 words
The method of claim 16, wherein said p-type dopant extends out laterally on opposite sides of said p-type ions, along a line passing through said p-type ions.
Claim 20
Dependent Claim
37 words
The method of claim 17, wherein said n-type dopant forms two regions which are on opposite sides of said p-type ions and lie on a second line passing through said p-type ions transversely to said first line.
Claim 21
Dependent Claim
25 words
The method of claim 18, wherein the doped regions made by said p-type and n-type dopants present a cruciform appearance as seen in plan view.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-21 | 1990-01-20 | 1990-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-21 | 1994-01-20 | 1994-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-21 | 1998-01-20 | 1998-07-22 | $7700.00 | Window Closed / Lapsed |