Patent US4596954A successfully refreshed from Google Patents.
US4596954A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency doubler with fifty percent duty cycle output signal
Assignee: AMI Semiconductor Inc
•
Filing: 1984-02-29
•
Granted: 1986-06-24
•
Expires: 2004-02-29
Abstract
Abstract A unique frequency doubler circuit is utilized which requires only a handful of standard components such as operational amplifier, logic gates, resistors, capacitors and switches. In contrast to certain prior art frequency doublers, frequency doublers constructed in accordance with the teachings of this invention do not require the use of a phase lock loop, thereby resulting in a substantial simplification of circuit construction. Furthermore, frequency doublers constructed in accordance with this invention utilize a feedback technique which assures that the duty cycle of the output signal will be 50%, or any other predefined value.
Inventors
- 👤 Yusuf A. Haque
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:16
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/00006; H03K5/156; H03K5/1565
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
184 words
A frequency doubler circuit comprising: an input terminal for receiving an input signal; an output terminal for providing an output signal having a frequency twice the frequency of said input signal; a delay means having an input lead connected to said input terminal and having an output terminal; an exclusive OR gate having a first input lead connected to said input terminal, a second input lead connected to said output lead of said delay means, and an output lead which provides an intermediate signal having twice the frequency of said input signal; and means for adjusting the duty cycle of said intermediate signal to equal a desired duty cycle; and wherein said means for adjusting comprises: means responsive to said intermediate signal which provides a ramp voltage to increase in magnitude; means for integrating said ramp voltage, providing an integrated voltage; means for comparing said ramp voltage and said integrated voltage, thereby providing a logical one output voltage when said ramp voltage is greater than said integrated voltage, and a logical zero output voltage when said ramp voltage is less than said integrated voltage.
Claim 2
Dependent Claim
184 words
A frequency doubler circuit comprising: an input terminal for receiving an input signal; an output terminal for providing an output signal having a frequency twice the frequency of said input signal; a delay means having an input lead connected to said input terminal and having an output terminal; an exclusive OR gate having a first input lead connected to said input terminal, a second input lead connected to said output lead of said delay means, and an output lead which provides an intermediate signal having twice the frequency of said input signal; and means for adjusting the duty cycle of said intermediate signal to equal a desired duty cycle; and wherein said means for adjusting comprises: means responsive to said intermediate signal which provides a ramp voltage to increase in magnitude; means for integrating said ramp voltage, providing an integrated voltage; means for comparing said ramp voltage and said integrated voltage, thereby providing a logical one output voltage when said ramp voltage is greater than said integrated voltage, and a logical zero output voltage when said ramp voltage is less than said integrated voltage.
Claim 3
Dependent Claim
39 words
The structure as in claim 1 wherein: said means for integrating is powered by a positive voltage source +Vref and a negative voltage source -Vref such that the duty cycle D of said output signal is defined as: D=(+Vref)/(|+Vref|+|-Vref|).
References Cited (Backward Citations)
US3593156A
Cited
US3601705A
Cited
US3710146A
Cited
US3622210A
Cited
US3648062A
Cited
US3721766A
Cited
US3668489A
Cited
US3742353A
Cited
US3786357A
Cited
US3764927A
Cited
US3721896A
Cited
US3771044A
Cited
US4048571A
Cited
US3947780A
Cited
US4042834A
Cited
US4101789A
Cited
US4052626A
Cited
US4051386A
Cited
US4077010A
Cited
US4439689A
Cited
US4446389A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-23 | 1989-12-23 | 1990-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-23 | 1993-12-23 | 1994-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-23 | 1997-12-23 | 1998-06-24 | $7700.00 | Window Closed / Lapsed |