US3786357A
Expired / Lapsed
US
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Digital pulse train frequency multiplier
Assignee: General Electric Co
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Filing: 1971-11-30
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Granted: 1974-01-15
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Expires: 1991-11-30
Abstract
Abstract A pair of digital differentiators respectively generate pulses at the leading and the trailing edges of an input pulse, doubling the pulse input frequency. This doubling is used for reduction of errors in digital transmission and for frequency multiplication by powers of two and by values other than powers of two.
Inventors
- 👤 Isle A Belle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:34
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/20; H03; H03B; H03B19/00; H03K; H03K5/00; H03K5/00006
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
182 words
A digital frequency multiplication system comprising: a. means for receiving a train of digital input pulses, each of said input pulses having a leading edge and a trailing edge, b. first digital differentiator means responsive to each leading edge for producing a corresponding pulse in a first train of pulses, c. second digital differentiator means responsive to each trailing edge for producing a corresponding pulse in a second train of pulses, d. each of said digital differentiator means comprising 1. a first path for transmitting said input pulses substantially without delay, 2. a second path for transmitting said input pulses with a predetermined delay, e. means for combining said first train of pulses and said second train of pulses to produce a third train of pulses having a pulse corresponding to each leading edge and a pulse corresponding to each trailing edge, said means for combining said first and second trains of pulses including means for inverting pulses in one of said digital differentiators, whereby said third train of pulses has a frequency double that of the train of digital input pulses.
Claim 2
Dependent Claim
182 words
A digital frequency multiplication system comprising: a. means for receiving a train of digital input pulses, each of said input pulses having a leading edge and a trailing edge, b. first digital differentiator means responsive to each leading edge for producing a corresponding pulse in a first train of pulses, c. second digital differentiator means responsive to each trailing edge for producing a corresponding pulse in a second train of pulses, d. each of said digital differentiator means comprising 1. a first path for transmitting said input pulses substantially without delay, 2. a second path for transmitting said input pulses with a predetermined delay, e. means for combining said first train of pulses and said second train of pulses to produce a third train of pulses having a pulse corresponding to each leading edge and a pulse corresponding to each trailing edge, said means for combining said first and second trains of pulses including means for inverting pulses in one of said digital differentiators, whereby said third train of pulses has a frequency double that of the train of digital input pulses.
Claim 3
Dependent Claim
90 words
a second path for transmitting said input pulses with a predetermined delay, e. means for combining said first train of pulses and said second train of pulses to produce a third train of pulses having a pulse corresponding to each leading edge and a pulse corresponding to each trailing edge, said means for combining said first and second trains of pulses including means for inverting pulses in one of said digital differentiators, whereby said third train of pulses has a frequency double that of the train of digital input pulses.
Claim 4
Dependent Claim
90 words
a second path for transmitting said input pulses with a predetermined delay, e. means for combining said first train of pulses and said second train of pulses to produce a third train of pulses having a pulse corresponding to each leading edge and a pulse corresponding to each trailing edge, said means for combining said first and second trains of pulses including means for inverting pulses in one of said digital differentiators, whereby said third train of pulses has a frequency double that of the train of digital input pulses.
Claim 5
Dependent Claim
65 words
A system according to claim 1 wherein said means for combining said first and second trains of pulses further comprises an inverter connected between the means for receiving a train of digital input pulses and one of said digital differentiators To cause said one digital differentiator to be responsive to a different one of leading and trailing edge than it would otherwise be responsive to.
Claim 6
Dependent Claim
97 words
A system according to claim 1 wherein, a. said first path comprises a first inverter, said first inverter receiving said input pulses and providing an inverted output, b. said second path comprises a capacitor, a second inverter connected to receive said input pulses and to provide an intermediate inverted output across said capacitor, and a third inverter receiving an input signal from said capacitor, providing a delayed noninverted version of said input pulses, c. said combining means comprises a two-input NAND gate fed by the output of said first inverter and the output of said second inverter.
Claim 7
Dependent Claim
20 words
A system according to claim 3 wherein each of said inverters comprises a NAND gate having its inputs tied together.
Claim 8
Dependent Claim
166 words
A system according to claim 1 wherein the minimum time from leading edge to next leading edge of pulses in said train of digital input pulses is T and wherein the time from leading edge to trailing edge of pulses in said train of digital input pulses is substantially one-half T, further comprising: a. means for transmitting said third train of pulses through a noisy transmission channel to provide a fourth train of pulses including the pulses of the third train plus added error pulses, b. means for initiating pulses of width W, where W is longer than or equal to one-half T but shorter than T, whenever a pulse of width W does not currently exist and simultaneously a pulse occurs in said fourth train, and c. means for initiating pulses of width substantially one-half T whenever a pulse of width one-half T does not currently exist and simultaneously a pulse of width W exists and simultaneously a pulse is initiated in said fourth train.
Claim 9
Dependent Claim
41 words
A system according to claim 1 for multiplication by a number other than two further comprising an additional frequency doubler connected to receive said third train as its input, whereby to redouble the frequency of the pulses in the third train.
Claim 10
Dependent Claim
35 words
A system according to claim 6 wherein an inherent delay in each of the first and second digital differentiators is greater than an inherent delay used for a corresponding purpose in the additional frequency doubler.
Claim 11
Dependent Claim
53 words
A system according to claim 6 further comprising: a. a countdown counter preloaded with a given number and counted down by pulses of some frequency redoubled a predetermined number of times, and b. a coincidence gate for providing an output when the counter counts down to zero and a redoubled frequency pulse occurs.
References Cited (Backward Citations)
US3002152A
Cited
US3345584A
Cited
US3479603A
Cited
US3504288A
Cited
US3571725A
Cited
US3541456A
Cited
US3546601A
Cited
US3543295A
Cited
US3601636A
Cited
US3634771A
Cited
US3673434A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-14 | 1977-07-16 | 1978-01-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-14 | 1981-07-16 | 1982-01-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-14 | 1985-07-16 | 1986-01-15 | $7700.00 | Window Closed / Lapsed |