US4051386A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency doubling circuit
Assignee: National Semiconductor Corp
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Filing: 1976-07-22
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Granted: 1977-09-27
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Expires: 1996-07-22
Abstract
Abstract A frequency doubler circuit uses a single capacitor which is initially charged. A pair of switches is sequentially actuated so that each switch acts to first discharge the capacitor and then charge it in the opposite polarity. The switches are sequentially actuated from a differential input amplifier. Thus each input cycle will actuate both switches so as to discharge and charge the capacitor twice. Output logic senses the capacitor cycling and produces two output pulses for each input cycle.
Inventors
- 👤 David K. Long
- 👤 Robert W. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:33
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/00006
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
244 words
A frequency doubling circuit having an input for accommodating an input signal, including driver means responsive to said input signal for operating said circuit and means for coupling said circuit to first and second power supply terminals, said circuit comprising: a capacitor having first and second terminals; a first switching transistor having a collector coupled to said first capacitor terminal, an emitter coupled to said first power supply terminal, and a base coupled to said driver means; a second switching transistor having an emitter coupled to said second capacitor terminal, a collector coupled to said second power supply terminal and a base coupled to said base of said first switching transistors; a third switching transistor having a collector coupled to said second capacitor terminal, an emitter coupled to said first power supply terminal and a base coupled to said driver means; a fourth switching transistor having an emitter coupled to said first capacitor terminal, a collector coupled to said second power supply terminal, and a base coupled to said base of said third switching transistor; resistive means coupling each terminal of said capacitor to said second power supply terminal; means in said driver means for driving said fist and second switching transistor bases in phase opposition to said third and fourth switching transistor bases in response to said input signal; and output logic means coupled to said terminals of said capacitors whereby two output pulses are produced for each cycle of said input signal.
Claim 2
Dependent Claim
244 words
A frequency doubling circuit having an input for accommodating an input signal, including driver means responsive to said input signal for operating said circuit and means for coupling said circuit to first and second power supply terminals, said circuit comprising: a capacitor having first and second terminals; a first switching transistor having a collector coupled to said first capacitor terminal, an emitter coupled to said first power supply terminal, and a base coupled to said driver means; a second switching transistor having an emitter coupled to said second capacitor terminal, a collector coupled to said second power supply terminal and a base coupled to said base of said first switching transistors; a third switching transistor having a collector coupled to said second capacitor terminal, an emitter coupled to said first power supply terminal and a base coupled to said driver means; a fourth switching transistor having an emitter coupled to said first capacitor terminal, a collector coupled to said second power supply terminal, and a base coupled to said base of said third switching transistor; resistive means coupling each terminal of said capacitor to said second power supply terminal; means in said driver means for driving said fist and second switching transistor bases in phase opposition to said third and fourth switching transistor bases in response to said input signal; and output logic means coupled to said terminals of said capacitors whereby two output pulses are produced for each cycle of said input signal.
Claim 3
Dependent Claim
13 words
The circuit of claim 1 wherein said driver means comprise a differential amplifier.
Claim 4
Dependent Claim
115 words
The circuit of claim 2 wherein said logic means comprise three transistors having parallel emitter collector circuits, a constant current source between the emitters and said first power supply terminal, means coupling the collectors to said second power supply terminal and three base terminals; means coupling the first of said three base terminals to said first capacitor terminal; means coupling the second of said terminals to said second capacitor terminal; means coupling the third of said three base three base terminals to a predetermined potential intermediate between the potential difference of said power supply terminals; and mean for producing an output signal in response to the current flowing in the third of said three transistors.
Claim 5
Dependent Claim
29 words
The circuit of claim 3 wherein said last named means comprises resistive means coupling said collector of said third of said three transistors to said second power supply terminal.
Claim 6
Dependent Claim
31 words
The circuit of claim 3 wherein said last named means comprises a current source coupled between said collector of said third of said three transistors and said second power supply terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-09-26 | 1981-03-28 | 1981-09-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-09-26 | 1985-03-28 | 1985-09-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-09-26 | 1989-03-28 | 1989-09-27 | $7700.00 | Window Closed / Lapsed |