Patent US4596068A successfully refreshed from Google Patents.
US4596068A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for minimizing boron depletion in N-channel FET at the silicon-silicon oxide interface
Assignee: Intersil Corp
•
Filing: 1983-12-28
•
Granted: 1986-06-24
•
Expires: 2003-12-28
Abstract
Abstract The surface of the channel and top gates of N channel IGFETS and JFETS respectively are compensated after a high temperature processing by ion implanting boron through a protective layer. The peak impurity concentration is to occur in a sacrificial gate pad oxide layer to ensure a predictable dopant concentration in the substrate.
Inventors
- 👤 Solomon F. Peters, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:18
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D30/00; H10D30/60; H10D30/637; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/328; H10P30/21; H10P30/212; Y; Y10; Y10S; Y10S148/00; Y10S148/018
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
145 words
A method for the manufacture of uniform NJFET structures, comprising: doping a portion of a substrate with boron a first time to the desired final dopant level for a background P-type gate region of the substrate in which an NJFET is to be formed; thereafter conducting all remaining high-temperature processing which is to be followed by the steps of; forming a first protective layer on the surface of said substrate; doping said portion of said substrate by ion-implantation with boron a second time to increase the boron concentration at the surface region of the substrate to a substantially uniform value with the peak concentration in said first protective layer; removing said first protective layer; forming a second protective layer on the surface of said substrate; and doping said substrate by ion-implantation with an N-type dopant to form an N-channel below the surface of said substrate.
Claim 2
Independent Claim
145 words
A method for the manufacture of uniform NJFET structures, comprising: doping a portion of a substrate with boron a first time to the desired final dopant level for a background P-type gate region of the substrate in which an NJFET is to be formed; thereafter conducting all remaining high-temperature processing which is to be followed by the steps of; forming a first protective layer on the surface of said substrate; doping said portion of said substrate by ion-implantation with boron a second time to increase the boron concentration at the surface region of the substrate to a substantially uniform value with the peak concentration in said first protective layer; removing said first protective layer; forming a second protective layer on the surface of said substrate; and doping said substrate by ion-implantation with an N-type dopant to form an N-channel below the surface of said substrate.
Claim 3
Dependent Claim
17 words
The method of claim 1, wherein said first protective layer is an oxide 1,000-2,000 Angstroms in thickness.
Claim 4
Dependent Claim
17 words
The method of claim 1, wherein said second protective layer is an oxide 300-1,000 Angstroms in thickness.
Claim 5
Dependent Claim
24 words
The method of claim 1, wherein said peak N-type doping is to a depth of about 3,000 Angstroms below the surface of said substrate.
Claim 6
Dependent Claim
12 words
The method of claim 1, wherein said substrate is comprised of silicon.
Claim 7
Dependent Claim
11 words
The method of claim 1, wherein said N-type dopant is phosphorus.
Claim 8
Dependent Claim
21 words
The method of claim 1, wherein said high-temperature processing includes forming source and drain regions in said portion of said substrate.
Claim 9
Dependent Claim
19 words
The method of claim 7, wherein said high-temperature processing further includes forming base and emitter regions of bipolar transistors.
Claim 10
Independent Claim
128 words
A method of manufacture of uniform N-channel IGFET structures comprising: doping a portion of a substrate with boron to the desired final dopant level for a region of the substrate in which an N-channel IGFET is to be formed; thereafter conducting all remaining high-temperature processing which is to be followed by the steps of; forming a protective layer on the surface of said substrate; doping said portion of said substrate with boron a second time to increase the boron concentration at the surface region of the substrate to a substantially uniform value within said region and the peak concentration being in said protective layer; removing said protective layer; forming a gate insulation layer on the surface of said region; and forming a gate on said gate insulation layer.
Claim 11
Independent Claim
128 words
A method of manufacture of uniform N-channel IGFET structures comprising: doping a portion of a substrate with boron to the desired final dopant level for a region of the substrate in which an N-channel IGFET is to be formed; thereafter conducting all remaining high-temperature processing which is to be followed by the steps of; forming a protective layer on the surface of said substrate; doping said portion of said substrate with boron a second time to increase the boron concentration at the surface region of the substrate to a substantially uniform value within said region and the peak concentration being in said protective layer; removing said protective layer; forming a gate insulation layer on the surface of said region; and forming a gate on said gate insulation layer.
Claim 12
Dependent Claim
22 words
The method of claim 9, wherein said high temperature processing includes forming source and drain regions in said portion of said substrate.
Claim 13
Dependent Claim
27 words
The method of claim 9, including ion implanting an N-type dopant at a low temperature to form source and drains using said gate as an alignment mask.
Claim 14
Dependent Claim
19 words
The method of claim 10, wherein said high-temperature processing further includes forming base and emitter regions of bipolar transistors.
References Cited (Backward Citations)
US3523042A
Cited
US3607449A
Cited
US3799813A
Cited
US4021835A
Cited
US4075754A
Cited
US3899363A
Cited
US4000504A
Cited
US4074301A
Cited
US4047974A
Cited
US4106953A
Cited
US4185291A
Cited
US4276095A
Cited
US4242691A
Cited
US4434543A
Cited
US4422885A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-23 | 1989-12-23 | 1990-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-23 | 1993-12-23 | 1994-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-23 | 1997-12-23 | 1998-06-24 | $7700.00 | Window Closed / Lapsed |