US4021835A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device and a method for fabricating the same
Assignee: Hitachi Ltd
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Filing: 1975-01-27
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Granted: 1977-05-03
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Expires: 1995-01-27
Abstract
Abstract A MOS-FET (Metal-Oxide-Semiconductor Field Effect Transistor) comprises a semiconductor body, source and drain regions disposed in the body at portions separated from each other, a second semiconductor region having a higher impurity concentration than that of the body, formed by ion implantation in the body between the source and drain regions, a first semiconductor region having a lower impurity concentration than that of the second semiconductor region but a higher impurity concentration than that of the body, and having an opposite conductivity type to that of the second semiconductor region, formed by ion implantation, so that the second semiconductor region is very thin, and which has a very small amount of a minute current, that is a tailing current.
Inventors
- 👤 Jun Etoh
- 👤 Toshiaki Masuhara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:14
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D30/00; H10D30/60; H10D30/637; H10P30/21; H10P30/212
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
249 words
A semiconductor device comprising: a semiconductor body having one of p and n conductivity types; a source region of an opposite conductivity type to that of said semiconductor body, disposed in a first surface portion of said semiconductor body; a drain region of the same conductivity type as that of said source region, disposed in a second surface portion of said semiconductor body, spaced apart from said first surface portion of said semiconductor body in which said source region is disposed; a first semiconductor region, whose conductivity type is opposite to that of said semiconductor body, whose impurity concentration is higher than that of said semiconductor body and whose impurity dosage is within a range between 2 × 10 8 cm - 2 and 1 × 10 10 cm - 2 , disposed within said semiconductor body between said source and drain regions; a second semiconductor region whose conductivity type is opposite to that of said first semiconductor region, whose impurity concentration is higher than that of said first semiconductor region and whose impurity dosage is within a range between 6.6 × 10 10 cm - 2 and 1.2 × 10 12 cm - 2 , disposed in said semiconductor body between said source and drain regions and directly upon said first semiconductor region; an insulating layer disposed on the surface of said semiconductor body between said source and drain regions; a gate electrode disposed on said insulating layer; and electrodes connected to said source and drain regions, respectively.
Claim 2
Dependent Claim
249 words
A semiconductor device comprising: a semiconductor body having one of p and n conductivity types; a source region of an opposite conductivity type to that of said semiconductor body, disposed in a first surface portion of said semiconductor body; a drain region of the same conductivity type as that of said source region, disposed in a second surface portion of said semiconductor body, spaced apart from said first surface portion of said semiconductor body in which said source region is disposed; a first semiconductor region, whose conductivity type is opposite to that of said semiconductor body, whose impurity concentration is higher than that of said semiconductor body and whose impurity dosage is within a range between 2 × 10 8 cm - 2 and 1 × 10 10 cm - 2 , disposed within said semiconductor body between said source and drain regions; a second semiconductor region whose conductivity type is opposite to that of said first semiconductor region, whose impurity concentration is higher than that of said first semiconductor region and whose impurity dosage is within a range between 6.6 × 10 10 cm - 2 and 1.2 × 10 12 cm - 2 , disposed in said semiconductor body between said source and drain regions and directly upon said first semiconductor region; an insulating layer disposed on the surface of said semiconductor body between said source and drain regions; a gate electrode disposed on said insulating layer; and electrodes connected to said source and drain regions, respectively.
Claim 3
Dependent Claim
31 words
A semiconductor device according to claim 1, wherein the first and second semiconductor regions have thicknesses within ranges between 200 A and 1000 A, and 100 A and 1800 A, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-05-02 | 1980-11-01 | 1981-05-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-05-02 | 1984-11-01 | 1985-05-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-05-02 | 1988-11-01 | 1989-05-03 | $7700.00 | Window Closed / Lapsed |