US4185291A
Expired / Lapsed
US
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Junction-type field effect transistor and method of making the same
Assignee: Panasonic Holdings Corp
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Filing: 1978-06-16
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Granted: 1980-01-22
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Expires: 1998-06-16
Abstract
Abstract A junction-type FET comprising a semiconductor substrate 21 of a first conductivity type, and island region 22 of a second conductivity type which comprises a channel region and is selectively formed in the semiconductor substrate 21, and a buried isolating region 27 which is selected from the group consisting of an intrinsic layer, a low impurity concentration layer of the second conductivity type and a layer of first conductivity type, the buried isolating layer being formed by ion implantation of impurities of the first conductivity type in the island region 22 while keeping the impurity concentration at the surface thereof relatively high, and the buried isolating layer substantially isolating the channel region from the surface.
Inventors
- 👤 Takashi Hirao
- 👤 Shigetoshi Takayanagi
- 👤 Takeshi Onuma
- 👤 Toshio Sugawa
- 👤 Kaoru Inoue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:19
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/83
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
195 words
A junction-type FET comprising a semiconductor substrate of a first conductivity type, an island region of a second conductivity type opposite to said first conductivity type which island region is selectively formed in said semiconductor substrate with its top surface contiguous to the top surface of said substrate, a spaced source region and drain region of a high impurity concentration of said second conductivity type selectively formed in said island region, a gate region of a high impurity concentration of said first conductivity type selectively formed between said source region and said drain region in said island region with its bottom shallower than the bottom of said island region, a buried isolating region which is selected from the group consisting of an intrinsic layer and a low impurity concentration layer of said second conductivity type, which is formed at a specified depth shallower than the bottom of said gate region between said source region and said drain region in said island region, and which is disposed substantially parallel to said surface of said island region to divide said island region into a surface region and a channel region which is under the buried insulating region.
Claim 2
Dependent Claim
195 words
A junction-type FET comprising a semiconductor substrate of a first conductivity type, an island region of a second conductivity type opposite to said first conductivity type which island region is selectively formed in said semiconductor substrate with its top surface contiguous to the top surface of said substrate, a spaced source region and drain region of a high impurity concentration of said second conductivity type selectively formed in said island region, a gate region of a high impurity concentration of said first conductivity type selectively formed between said source region and said drain region in said island region with its bottom shallower than the bottom of said island region, a buried isolating region which is selected from the group consisting of an intrinsic layer and a low impurity concentration layer of said second conductivity type, which is formed at a specified depth shallower than the bottom of said gate region between said source region and said drain region in said island region, and which is disposed substantially parallel to said surface of said island region to divide said island region into a surface region and a channel region which is under the buried insulating region.
Claim 3
Dependent Claim
25 words
A junction-type FET in accordance with claim 1, wherein the impurity concentration in said island region is maximum at the surface of said semiconductor substrate.
Claim 4
Dependent Claim
23 words
A junction-type FET in accordance with claim 1, wherein said isolating region is an ion-implanted region containing impurities of said second conductivity type.
Claim 5
Dependent Claim
22 words
A junction-type FET in accordance with claim 1, wherein said isolating region is a high resistivity region of said second conductivity type.
Claim 6
Dependent Claim
37 words
A junction-type FET of claim 1, wherein said buried isolating region is divided into two parts, one disposed on one side of the gate region and the other disposed on the other side of the gate region.
Claim 7
Dependent Claim
25 words
A junction-type FET in accordance with claim 5, wherein the impurity concentration in said island region is maximum at the surface of said semiconductor substrate.
Claim 8
Dependent Claim
23 words
A junction-type FET in accordance with claim 5, wherein said isolating region is an ion-implanted region containing impurities of said second conductivity type.
Claim 9
Dependent Claim
42 words
A junction-type FET in accordance with claim 5, wherein said intrinsic layer is formed shallower than the deepest part of said gate region, and divides said island region into a surface region and a channel region which is under said intrinsic layer.
Claim 10
Dependent Claim
22 words
A junction-type FET in accordance with claim 5, wherein said isolating region is a high resistivity region of said second conductivity type.
Claim 11
Dependent Claim
206 words
A junction-type FET comprising a semiconductor substrate of a first conductivity type, an island region of a second conductivity type opposite to said first conductivity type which island region is selectively formed in said semiconductor substrate with its top surface contiguous to the top surface of said substrate, a spaced source region and drain region of a high impurity concentration of said second conductivity type selectively formed in said island region, a gate region of a high impurity concentration of said first conductivity type selectively formed between said source region and said drain region in said island region, with its bottom shallower than the bottom of said island region, a buried isolating region of a high impurity concentration layer of said first conductivity type formed at a specified depth shallower than the bottom of said gate region between said source region and said drain region in said island region, and which buried isolating region contacts with said source region and said drain region and is spaced from said gate region by a predetermined distance, and is disposed substantially parallel to said surface of said island region to divide said island region into a surface region and a channel region which is under said buried isolating region.
Claim 12
Dependent Claim
206 words
A junction-type FET comprising a semiconductor substrate of a first conductivity type, an island region of a second conductivity type opposite to said first conductivity type which island region is selectively formed in said semiconductor substrate with its top surface contiguous to the top surface of said substrate, a spaced source region and drain region of a high impurity concentration of said second conductivity type selectively formed in said island region, a gate region of a high impurity concentration of said first conductivity type selectively formed between said source region and said drain region in said island region, with its bottom shallower than the bottom of said island region, a buried isolating region of a high impurity concentration layer of said first conductivity type formed at a specified depth shallower than the bottom of said gate region between said source region and said drain region in said island region, and which buried isolating region contacts with said source region and said drain region and is spaced from said gate region by a predetermined distance, and is disposed substantially parallel to said surface of said island region to divide said island region into a surface region and a channel region which is under said buried isolating region.
Claim 13
Dependent Claim
25 words
A junction-type FET in accordance with claim 10, wherein the impurity concentration in said island region is maximum at the surface of said semiconductor substrate.
Claim 14
Dependent Claim
23 words
A junction-type FET in accordance with claim 10, wherein said isolating region is an ion-implanted region containing impurities of said second conductivity type.
Claim 15
Dependent Claim
42 words
A junction-type FET in accordance with claim 10, wherein said intrinsic layer is formed shallower than the deepest part of said gate region, and divides said island region into a surface region and a channel region which is under said intrinsic layer.
Claim 16
Dependent Claim
22 words
A junction-type FET in accordance with claim 10, wherein said isolating region is a high resistivity region of said second conductivity type.
Claim 17
Independent Claim
157 words
A method of making a junction-type FET comprising the steps of: in a substrate of a first conductivity type, forming an island region of a second conductivity type, forming a source and a drain region of a high impurity concentration and of said second conductivity type in said island region, forming a buried isolating region in said island region by an ion implantation of impurities of said first conductivity type from the front face of said island region in a manner to have maximum impurity concentration at the position of specified uniform depth from said surface of said island region and to offset the impurity of the second conductivity type, and forming a gate region of a high impurity concentration and of a first conductivity type between said source region and said drain region in said isolating region, said gate region being shallower than the bottom of said island region and deeper than said buried isolating region.
Claim 18
Independent Claim
157 words
A method of making a junction-type FET comprising the steps of: in a substrate of a first conductivity type, forming an island region of a second conductivity type, forming a source and a drain region of a high impurity concentration and of said second conductivity type in said island region, forming a buried isolating region in said island region by an ion implantation of impurities of said first conductivity type from the front face of said island region in a manner to have maximum impurity concentration at the position of specified uniform depth from said surface of said island region and to offset the impurity of the second conductivity type, and forming a gate region of a high impurity concentration and of a first conductivity type between said source region and said drain region in said isolating region, said gate region being shallower than the bottom of said island region and deeper than said buried isolating region.
Claim 19
Independent Claim
149 words
A method of making a junction-type FET comprising the steps of: in a substrate of a first conductivity type, forming an island region of a second conductivity type, forming a source and a drain region of a high impurity concentration and of said second conductivity type in said island region, forming a gate region of a high impurity concentration and of a first conductivity type shallower than the bottom of said island region, between said source region and said drain region, and forming an isolating region shallower than the bottom of said gate region in said island region by an ion implantation of impurities of said first conductivity type from the front face of said island region in a manner to have maximum impurity concentration at the position of specified uniform depth from said surface of said island region and to offset the impurity of the second conductivity type.
Claim 20
Independent Claim
149 words
A method of making a junction-type FET comprising the steps of: in a substrate of a first conductivity type, forming an island region of a second conductivity type, forming a source and a drain region of a high impurity concentration and of said second conductivity type in said island region, forming a gate region of a high impurity concentration and of a first conductivity type shallower than the bottom of said island region, between said source region and said drain region, and forming an isolating region shallower than the bottom of said gate region in said island region by an ion implantation of impurities of said first conductivity type from the front face of said island region in a manner to have maximum impurity concentration at the position of specified uniform depth from said surface of said island region and to offset the impurity of the second conductivity type.
Claim 21
Dependent Claim
42 words
A method of making a junction-type FET of claim 15, wherein said buried isolating region is formed divided into two parts, one disposed on one side of the gate region and the other disposed on the other side of the gate region.
Claim 22
Dependent Claim
42 words
A method of making a junction-type FET of claim 16, wherein said buried isolating region is formed divided into two parts, one disposed on one side of the gate region and the other disposed on the other side of the gate region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-01-21 | 1983-07-23 | 1984-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-01-21 | 1987-07-23 | 1988-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-01-21 | 1991-07-23 | 1992-01-22 | $7700.00 | Window Closed / Lapsed |