Patent US2040053A successfully refreshed from Google Patents.
Patent US4583179A successfully refreshed from Google Patents.
US4583179A
Expired / Lapsed
US
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Semiconductor integrated circuit
Assignee: Fujitsu Ltd
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Filing: 1982-12-29
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Granted: 1986-04-15
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Expires: 2002-12-29
Abstract
Abstract A semiconductor integrated circuit which includes therein at least one inspection circuit for inspecting a voltage level produced at an internal node to be inspected. The inspection circuit has at least a control signal input portion connected to the internal node to be inspected and an input part connected to an external input/output pin. The inspection circuit includes a series-connected transistor and diode connected between a power source and the input portion, a capacitor connected between a gate of the transistor and the input portion, and a transfer gate transistor connected between the control signal input portion and the gate of the transistor. The inspection circuit discriminates the level at the internal node according to a flow or nonflow of a current, via the external input/output pin, when a particular signal having a voltage level higher than the power source level is supplied to the external input/output pin.
Inventors
- 👤 Takashi Horii
- 👤 Tomio Nakano
- 👤 Masao Nakano
- 👤 Norihisa Tsuge
- 👤 Junji Ogawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:42
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/835; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
190 words
A semiconductor integrated circuit including therein at least an internal node to be inspected, at which node either ground level or a power source level is produced, and including a plurality of external input/output pins, said semiconductor integrated circuit comprising: at least one inspection circuit for discriminating the level of the power source level or ground level produced at the internal node, according to a flow or non-flow of current via the external input/output pins when a particular signal having a voltage level higher than the power source level is supplied to the external input/output pins, said inspection circuit comprising: a control signal input portion operatively connected to the internal node to be inspected; an input portion operatively connected to a particular one of said plurality of external input/output pins; a transistor operatively connected to the power source level, said transistor having a gate; a diode operatively connected in series with said transistor and said input portion; a capacitor operatively connected between the gate of said transistor and said input portion; and a transfer gate transistor operatively connected between said control signal input portion and the gate of said transistor.
Claim 2
Dependent Claim
190 words
A semiconductor integrated circuit including therein at least an internal node to be inspected, at which node either ground level or a power source level is produced, and including a plurality of external input/output pins, said semiconductor integrated circuit comprising: at least one inspection circuit for discriminating the level of the power source level or ground level produced at the internal node, according to a flow or non-flow of current via the external input/output pins when a particular signal having a voltage level higher than the power source level is supplied to the external input/output pins, said inspection circuit comprising: a control signal input portion operatively connected to the internal node to be inspected; an input portion operatively connected to a particular one of said plurality of external input/output pins; a transistor operatively connected to the power source level, said transistor having a gate; a diode operatively connected in series with said transistor and said input portion; a capacitor operatively connected between the gate of said transistor and said input portion; and a transfer gate transistor operatively connected between said control signal input portion and the gate of said transistor.
Claim 3
Dependent Claim
28 words
A semiconductor integrated circuit as set forth in claim 1, wherein the particular signal has a voltage level higher than the power source level by substantially 2 V.
Claim 4
Dependent Claim
63 words
A semiconductor integrated circuit as set forth in claim 1, wherein when n (where n is an integer greater than 2) internal nodes exist in the semiconductor integrated circuit, n inspection circuits are provided for the internal nodes, said inspection circuits being independently connected to respective external input/output pins through which said inspection circuits are adapted to receive the higher voltage level signal.
Claim 5
Dependent Claim
81 words
A semiconductor integrated circuit as set forth in claim 3, operatively connected to receive input information, further comprising a read only memory operatively connected to said control input portion of said inspection circuit, said read only memory storing the input information and indicating that at least one of the internal nodes is a different voltage level, so that said flow or non-flow of current changes when compared to a case when all of the internal nodes indicate the same voltage level.
Claim 6
Dependent Claim
38 words
A semiconductor integrated circuit as set forth in claim 1, wherein when n (where n is an integer greater than 2) internal nodes exist in the semiconductor integrated circuit, said inspection circuit is connected to the internal nodes.
Claim 7
Dependent Claim
51 words
A semiconductor integrated circuit as set forth in claim 5, further comprising a multi-input OR gate, operatively connected to said inspection circuit, for receiving at its multi-input the voltage levels produced at the internal nodes and supplying a resultant output therefrom to said control signal input portion of said inspection circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-14 | 1989-10-14 | 1990-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-14 | 1993-10-14 | 1994-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-14 | 1997-10-14 | 1998-04-15 | $7700.00 | Window Closed / Lapsed |