CMOS substrate bias generator having only P channel transistors in the charge pump

Claim 2

A substrate bias generator for CMOS semiconductor circuitry having a charge pump to deliver a negative voltage VBB to the substrate, including: a first node and an output to the substrate; means for receiving a first oscillating signal having transitions between high and low values, said means being coupled to said first node; means for coupling said first node to said output; first selectively operable means for clamping said first node to a reference level having an on and an off state, said first selectively operable means being in an off state whenever there is a transition in said first oscillating signal; a second node coupled to said first means for clamping; means coupled to said second node for receiving a second oscillating signal having transitions between high and low values, said second oscillating signal being phase shifted from said first oscillating signal; and means for controlling the voltage range at said second node in steady state operation to essentially non-positive voltage.

Claim 3

The circuit of claim 1 wherein said means for controlling the voltage range at said second node includes: second selectively operable means for clamping said second node to said reference level; a third node; means for receiving a third oscillating signal coupled to said third node, said third oscillating signal being in phase with said first oscillating signal; said second means for clamping being responsively coupled to said third node.

Claim 4

The circuit of claim 2 wherein said means for controlling further includes: third selectively operable means for clamping said third node to said reference level, being responsively coupled to said second node.

Claim 5

The circuit of claim 3 wherein said means for clamping includes P channel MOS transistors coupled to said means for receiving said second and third oscillating signals.

Claim 6

The circuit of claim 2 wherein said means for coupling said first node to said output includes: a fourth node; selectively operable means for coupling said first node to said output, being responsively coupled to said fourth node; means for receiving a fourth oscillating signal, coupled to said fourth node, said fourth oscillating signal being in phase with said first oscillating signal.

Claim 7

The circuit of claim 5 further including: fourth selectively operable means for clamping said fourth node to said reference level; said fourth means for clamping being responsively coupled to said second node.

Claim 8

The circuit of claim 1 wherein said first means for clamping includes no N channel MOS device.

Claim 9

The circuit of claim 2 wherein each of said first and second means for clamping includes a P channel MOS device.

Claim 10

The circuit of claim 3 wherein each of said first, second and third means for clamping includes no N channel MOS device.

Claim 11

The circuit of claim 4 wherein each of said means for clamping includes no N channel MOS device.

Claim 12

The circuit of claim 5 wherein each of said means for clamping includes no N channel MOS device.

Claim 13

The circuit of claim 6 wherein each of said means for clamping includes no N channel MOS device.

Claim 14

The circuit according to claim 1 further including a generator for generating said oscillating signals, said generator including: a ring oscillator; first logic means coupled to said oscillator for generating a periodic signal having a first duty cycle, said signal constituting said first oscillating signal; and second logic means coupled to said oscillator for receiving periodic signals therefrom having a phase separation between them, for generating said second oscillating signal having a longer duty cycle than said first oscillating signal, said second oscillating signal being at a high level when said first oscillating signal is at a low level, said second oscillating signal being at a low level at selected times when said first oscillating signal is at a high level.

Claim 15

The circuit of claim 2 further including a generator for generating said oscillating signals, said generator including: a ring oscillator; first logic means coupled to said oscillator for generating a periodic signal and having a first duty cycle, said signal constituting said first oscillating signal; second logic means coupled to said oscillator for receiving periodic signals therefrom having a phase separation between them, for generating said second oscillating signal and having a longer duty cycle than said first oscillating signal, said second oscillating signal being at a high level when said first oscillating signal is at a low level, said second oscillating signal being at a low level at selected times when said first oscillating signal is at a high level; and third logic means coupled to receive periodic signals from said oscillator having a phase separation between them, for generating said third oscillating signal having a duty cycle longer than the duty cycle of said first oscillating signal, said third oscillating signal being at a high level at selected times when said first oscillating signal is at a high level and being at a low level at selected times when said first oscillating signal is at a low level.

Claim 16

The circuit according to claim 14 wherein said second and third oscillating signals have equal duty cycles and have a phase difference between them of 180°.

Claim 17

The circuit according to claim 5 including a generator for generating said oscillating signals, said generator including: a ring oscillator; first logic means coupled to said oscillator for generating a periodic signal having voltage levels substantially between 0 volts and VCC and having a first duty cycle, said signal constituting said first oscillating signal; second logic means coupled to said oscillator for receiving periodic signals therefrom having a phase separation between them, and for generating said second oscillating signal having voltage levels substantially between 0 volts and VCC and having a longer duty cycle than said first oscillating signal, said second oscillating signal being at a high level when said first oscillating signal is at a low level, said second oscillating signal being at a low level at selected times when said first oscillating signal is at a high level; and third logic means coupled to receive periodic signals therefrom having a phase separation between them, and for generating said third oscillating signal having voltage levels substantially between 0 volts and VCC and having a duty cycle longer than the duty cycle of said first oscillating signal, said third oscillating signal being at a high level at selected times when said first oscillating signal is at a high level and being at a low level at selected times when said first oscillating signal is at a low level.

Claim 18

The circuit according to claim 16 wherein said second and fourth oscillating signals have equal duty cycles and have a phase difference between them of 180°.

Claim 19

A CMOS substrate bias generator including: a PMOS charge pump; a regulator for controlling the operation of said substrate bias generator, including: an input circuit coupled to receive a VBB signal representative of the substrate bias voltage wherein said input circuit develops a voltage at a first node by gating a transistor with said VBB signal to regulate a current flow from VCC to ground; a reference circuit providing a reference voltage and including a voltage divider coupled to receive a VCC input; a comparison circuit coupled to said input circuit and to said reference circuit for comparing voltage levels therein; and output means responsively coupled to said comparison circuit to provide a signal to said substrate bias generator.

Claim 20

A CMOS substrate bias generator including: a PMOS charge pump; a regulator for controlling the operation of said substrate bias generator, including: an input circuit coupled to receive a VBB signal representative of the substrate bias voltage wherein said input circuit develops a voltage at a first node by gating a transistor with said VBB signal to regulate a current flow from VCC to ground; a reference circuit providing a reference voltage and including a voltage divider coupled to receive a VCC input; a comparison circuit coupled to said input circuit and to said reference circuit for comparing voltage levels therein; and output means responsively coupled to said comparison circuit to provide a signal to said substrate bias generator.

Claim 21

The combination of claim 18 wherein said comparison circuit includes hysteresis circuitry tending to preserve voltage at a node in said comparison circuit despite an imbalance between the signals applied thereto.

Claim 22

In combination, a CMOS substrate bias generator; a regulator for controlling the operation of said substrate bias generator, including: an input circuit coupled to receive a VBB signal representative of the substrate bias voltage; a reference circuit providing a reference voltage; a comparison circuit coupled to said input circuit and to said reference circuit for comparing voltage levels therein; a hysteresis circuit included in said comparison circuit tending to preserve voltage at a node in said comparison circuit despite an imbalance between the signals applied thereto; and output means responsively coupled to said comparison circuit for providing a signal to said substrate bias generator.

Claim 23

In combination, a CMOS substrate bias generator; a regulator for controlling the operation of said substrate bias generator, including: an input circuit coupled to receive a VBB signal representative of the substrate bias voltage; a reference circuit providing a reference voltage; a comparison circuit coupled to said input circuit and to said reference circuit for comparing voltage levels therein; a hysteresis circuit included in said comparison circuit tending to preserve voltage at a node in said comparison circuit despite an imbalance between the signals applied thereto; and output means responsively coupled to said comparison circuit for providing a signal to said substrate bias generator.

Claim 24

The combination of claim 20 wherein said input circuit develops a voltage at a first node by gating a transistor with said VBB signal to regulate a current flow from VCC to ground; and wherein said reference circuit includes a voltage divider coupled to receive a VCC input.