US4567575A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage level compensating interface circuit for inter-logic circuit data transmission system
Assignee: Sharp Corp
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Filing: 1985-04-26
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Granted: 1986-01-28
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Expires: 2005-04-26
Abstract
Abstract An interface circuit is disposed between an NMOS random access memory and a PMOS central processor unit in order to ensure accurate data transfer therebetween. The interface circuit includes a pull-up system for pulling up a signal transmission line to a desired voltage level. The pull-up system is energized when the data signal is transferred from the NMOS random access memory into the PMOS central processor unit. The pull-up operation is not conducted when the data signal is transferred from the PMOS central processor unit into the NMOS random access memory.
Inventors
- 👤 Mitsuo Morihisa
- 👤 Hideyuki Akao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 18:58
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/01855
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
235 words
A data signal transmission system in an electronic apparatus comprising: at least two semiconductor logic circuits; said at least two semiconductor logic circuits including: a first semiconductor logic circuit in which an output voltage level of a logic "high" bears a first voltage level; and a second semiconductor logic circuit in which an input voltage level of a logic "high" bears a second voltage level, wherein said second voltage level is higher than said first voltage level; interface circuit means disposed between said at least two semiconductor logic circuits for transferring data signals between said first and second semiconductor logic circuits in either direction; said interface circuit means consisting essentially of: a single signal transmission line interconnecting said first and second semiconductor circuits for transfer of each information bit; pull-up circuit means for pulling up said signal transmission line to a desired voltage level so that when said output voltage level of said first semiconductor logic circuit is a logic "high" the level on said signal transmission line is raised at least to said second voltage level; and a switching element operatively interconnected between said signal transmission line and said pull-up circuit means; and a control system for switching said switching element so that said signal transmission line is connected to said pull-up circuit means only when a said data signal is transferred from said first semiconductor logic circuit to said second semiconductor logic circuit.
Claim 2
Dependent Claim
235 words
A data signal transmission system in an electronic apparatus comprising: at least two semiconductor logic circuits; said at least two semiconductor logic circuits including: a first semiconductor logic circuit in which an output voltage level of a logic "high" bears a first voltage level; and a second semiconductor logic circuit in which an input voltage level of a logic "high" bears a second voltage level, wherein said second voltage level is higher than said first voltage level; interface circuit means disposed between said at least two semiconductor logic circuits for transferring data signals between said first and second semiconductor logic circuits in either direction; said interface circuit means consisting essentially of: a single signal transmission line interconnecting said first and second semiconductor circuits for transfer of each information bit; pull-up circuit means for pulling up said signal transmission line to a desired voltage level so that when said output voltage level of said first semiconductor logic circuit is a logic "high" the level on said signal transmission line is raised at least to said second voltage level; and a switching element operatively interconnected between said signal transmission line and said pull-up circuit means; and a control system for switching said switching element so that said signal transmission line is connected to said pull-up circuit means only when a said data signal is transferred from said first semiconductor logic circuit to said second semiconductor logic circuit.
Claim 3
Dependent Claim
27 words
The data signal transmission system of claim 1, wherein said first semiconductor logic circuit comprises a random access memory implemented with NMOS transistors of the enhancement mode.
Claim 4
Dependent Claim
29 words
The data signal transmission system of claim 1 or 2, wherein said second semiconductor logic circuit comprises a central processor unit implemented with PMOS transistors of the enhancement/depletion mode.
Claim 5
Dependent Claim
19 words
The data signal transmission system of claim 3, wherein said control system is included in said central processor unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-01-27 | 1989-07-29 | 1990-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-01-27 | 1993-07-29 | 1994-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-01-27 | 1997-07-29 | 1998-01-28 | $7700.00 | Window Closed / Lapsed |