US4110633A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Depletion/enhancement mode FET logic circuit
Assignee: International Business Machines Corp
•
Filing: 1977-06-30
•
Granted: 1978-08-29
•
Expires: 1997-06-30
Abstract
Abstract Disclosed is a field effect transistor (FET) logic circuit which advantageously combines enhancement and depletion mode field effect transistors. A depletion mode input transistor is connected between an input node and an intermediate node and has its gating electrode connected to a fixed potential such as ground. A self-biased depletion mode field effect load transistor is connected between a positive potential and the same intermediate node to which the gating electrode of one or more enhancement mode field effect transistors are also connected. The source electrodes of the enhancement mode field effect transistors are connected to a fixed source of potential such as ground while the drain electrodes of the enhancement mode field effect transistors provide open drain outputs to similarly constructed subsequent logic stages. A number of these open drain logic outputs may be connected together to form DOT logic configurations and the potential swing at these open drain outputs, being a function of the threshold voltage of the subsequent stage input device, is substantially less than the potential difference between the fixed positive and ground supply potentials.
Inventors
- 👤 Eugene M. Blaser
- 👤 Donald A. Conrad
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 05:44
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K19/09443
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
220 words
An improved field effect transistor logic circuit comprising: a first depletion mode input field effect transistor having its drain to source path connected between an input node and a first intermediate node and its gate electrode connected to a first fixed potential; a self biased second depletion mode field effect transistor connected as a load between a second fixed potential and said first intermediate node; at least one enhancement mode output field effect transistor having its gate electrode connected to said first intermediate node, its source electrode connected to said first fixed potential and its drain electrode connected to an output node having a substantial load capacitance associated therewith; and a third depletion mode field effect transistor having its drain to source path connected between a second intermediate node and the drain of said at least one enhancement mode output field effect transistor and its gate electrode connected to said first fixed potential; and a fourth depletion mode field effect transistor connected between said second fixed potential and said second intermediate node; whereby said output node connected to the drain electrode of said at least one enhancement mode output field effect transistor has a potential variable between said first fixed potential and another potential which is a function of the threshold voltage of said third depletion mode field effect transistor.
Claim 2
Dependent Claim
220 words
An improved field effect transistor logic circuit comprising: a first depletion mode input field effect transistor having its drain to source path connected between an input node and a first intermediate node and its gate electrode connected to a first fixed potential; a self biased second depletion mode field effect transistor connected as a load between a second fixed potential and said first intermediate node; at least one enhancement mode output field effect transistor having its gate electrode connected to said first intermediate node, its source electrode connected to said first fixed potential and its drain electrode connected to an output node having a substantial load capacitance associated therewith; and a third depletion mode field effect transistor having its drain to source path connected between a second intermediate node and the drain of said at least one enhancement mode output field effect transistor and its gate electrode connected to said first fixed potential; and a fourth depletion mode field effect transistor connected between said second fixed potential and said second intermediate node; whereby said output node connected to the drain electrode of said at least one enhancement mode output field effect transistor has a potential variable between said first fixed potential and another potential which is a function of the threshold voltage of said third depletion mode field effect transistor.
Claim 3
Dependent Claim
21 words
An improved field effect transistor logic circuit as in claim 1 wherein said second potential is higher than said first potential.
Claim 4
Dependent Claim
116 words
An improved field effect transistor logic circuit as in claim 2 further comprising: a fifth depletion mode field effect transistor having its drain to source path connected between another input node and a third intermediate node and its gate electrode connected to said first fixed potential; a self biased sixth depletion mode field effect transistor connected as a load between said second fixed potential and said third intermediate node; and another at least one enhancement mode output field effect transistor having its gate electrode connected to said third intermediate node, its source electrode connected to said first fixed potential and its drain electrode connected to said same output node having a substantial load capacitance associated therewith.
Claim 5
Dependent Claim
58 words
An improved field effect transistor logic circuit as in claim 3 comprising: an additional at least one enhancement mode output field effect transistor having its gate electrode connected to said second intermediate node, its source electrode connected to said first fixed potential and its drain electrode connected to another output node having a substantial load capacitance associated therewith.
Claim 6
Dependent Claim
163 words
An improved field effect transistor logic circuit comprising: a first input field effect transistor having its drain to source path connected between an input node and a first intermediate node and its gate electrode connected to a first fixed potential; a load field effect transistor having its drain to source path connected between a second fixed potential and said first intermediate node; a plurality of enhancement mode output field effect transistors having gate, source, and drain electrodes, their gate electrodes connected in common to said first intermediate node, their source electrodes connected to said first fixed potential; and a second input field effect transistor providing an input to a subsequent stage having its gate electrode connected to said first fixed potential and its drain to source path connected in an electrical path, including a load, between an output node formed by the drain electrode of at least one of said plurality of enhancement mode output field effect transistors and said second fixed potential.
Claim 7
Dependent Claim
163 words
An improved field effect transistor logic circuit comprising: a first input field effect transistor having its drain to source path connected between an input node and a first intermediate node and its gate electrode connected to a first fixed potential; a load field effect transistor having its drain to source path connected between a second fixed potential and said first intermediate node; a plurality of enhancement mode output field effect transistors having gate, source, and drain electrodes, their gate electrodes connected in common to said first intermediate node, their source electrodes connected to said first fixed potential; and a second input field effect transistor providing an input to a subsequent stage having its gate electrode connected to said first fixed potential and its drain to source path connected in an electrical path, including a load, between an output node formed by the drain electrode of at least one of said plurality of enhancement mode output field effect transistors and said second fixed potential.
Claim 8
Dependent Claim
25 words
An improved field effect transistor logic circuit as in claim 5 wherein said first, second, and load field effect transistors are of the depletion mode.
Claim 9
Dependent Claim
20 words
An improved field effect transistor logic circuit as in claim 6 wherein said load field effect transistor is self biased.
Claim 10
Dependent Claim
28 words
An improved field effect transistor logic circuit as in claim 5 wherein said second potential has a potential level higher than the potential level of said first potential.
Claim 11
Dependent Claim
39 words
An improved field effect transistor logic circuit as in claim 5 wherein said load comprises: another load field effect transistor connected between said second fixed potential and said second input field effect transistor and forming another intermediate node therewith.
Claim 12
Dependent Claim
58 words
An improved field effect transistor logic circuit as in claim 9 comprising: an additional at least one enhancement mode output field effect transistor having its gate electrode connected to said another intermediate node, its source electrode connected to said first fixed potential and its drain electrode connected to another output node having a substantial load capacitance associated therewith.
Claim 13
Dependent Claim
102 words
An improved field effect transistor logic circuit as in claim 5 further comprising: a third input field effect transistor having its drain to source path connected between another input node and a second intermediate node and its gate electrode connected to said first fixed potential; a second load field effect transistor connected between said second fixed potential and said second intermediate node; and another at least one enhancement mode output field effect transistor having its gate electrode connected to said second intermediate node, its source electrode connected to said first fixed potential and its drain electrode connected to said same output node.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-08-28 | 1982-02-27 | 1982-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-08-28 | 1986-02-27 | 1986-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-08-28 | 1990-02-27 | 1990-08-29 | $7700.00 | Window Closed / Lapsed |