US4564943A
Expired / Lapsed
US
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System path stressing
Assignee: International Business Machines Corp
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Filing: 1983-07-05
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Granted: 1986-01-14
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Expires: 2003-07-05
Abstract
Abstract In a data processing system in which data is sent over a data path between at least first and second devices, a clock distribution network is provided with the capability of selectively delaying the clock signal to either the sending or receiving devices to stress the short and long data paths.
Inventors
- 👤 John C. Collins
- 👤 John J. DeFazio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:00
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G01R31/2832; G01R31/2834; G06; G06F; G06F1/00; G06F1/04
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
107 words
In a data processing system having at least a first device providing output data to a data path in response to a first clock signal, and a second device storing input data from said dath path in response to a second clock signal, a system clock control apparatus for providing said first and second clock signals to said first and second devices, said system clock control apparatus comprising path stressing means for varying the timing relationships between said first and second clock signals, said path stressing means comprising delay means for selectively delaying either one of said first and second clock signals with respect to the other.
Claim 2
Dependent Claim
107 words
In a data processing system having at least a first device providing output data to a data path in response to a first clock signal, and a second device storing input data from said dath path in response to a second clock signal, a system clock control apparatus for providing said first and second clock signals to said first and second devices, said system clock control apparatus comprising path stressing means for varying the timing relationships between said first and second clock signals, said path stressing means comprising delay means for selectively delaying either one of said first and second clock signals with respect to the other.
Claim 3
Dependent Claim
59 words
A system clock control apparatus as defined in claim 1, wherein said path stressing means comprises control means for generating a control signal representing which of said first and second signals is said one signal and the amount of a desired delay, said delay means receiving said control signal and delaying said one signal by said desired delay amount.
Claim 4
Dependent Claim
22 words
A system clock control apparatus as defined in claim 2, wherein said first and second devices each comprise a shift register latch.
Claim 5
Dependent Claim
27 words
A system clock control apparatus as defined in claim 2, wherein said first device comprises a shift register latch and said second device comprises a memory array.
Claim 6
Dependent Claim
58 words
A system clock control apparatus as defined in claim 2, wherein said delay means comprises: a decoder for receiving said control signal and decoding said control signal into a decoder output, and first and second clock signal stressing means coupled to said decoder output and delaying their respective clock signals by amounts in accordance with said decoder output.
Claim 7
Dependent Claim
116 words
A system clock control apparatus as defined in claim 2, wherein said delay means comprises a first plurality of clock signal paths having inputs commonly connected to said first clock signal, and providing a first common output, each of said first plurality of clock signal paths delaying said first clock signal by a different amount, a second plurality of clock signal paths having inputs commonly receiving said second clock signal and providing a second common output, each of said second plurality of clock signal paths delaying said second clock signal by a different amount, and means for selectively enabling one of said first and second pluralities of clock signal paths in accordance with said decoder output.
Claim 8
Dependent Claim
151 words
In a data processing system of the type having at least a first device providing a data output to a data path in response to a first clock signal and a second device for storing input data from said data path in response to a second clock signal, a method of stressing said data path, said method comprising the steps of: decreasing the time interval between said first clock signal and said second clock signal, to thereby decrease the long path limit of said data path, whereby the long path limit is the maximum allowable propagation time over said data path between said first and second devices; and increasing the time interval between said first and second clock signals, to thereby increase the short path limit of said data path, where the short path limit is the minimum allowable propagation time over said data path between said first and second devices.
Claim 9
Dependent Claim
151 words
In a data processing system of the type having at least a first device providing a data output to a data path in response to a first clock signal and a second device for storing input data from said data path in response to a second clock signal, a method of stressing said data path, said method comprising the steps of: decreasing the time interval between said first clock signal and said second clock signal, to thereby decrease the long path limit of said data path, whereby the long path limit is the maximum allowable propagation time over said data path between said first and second devices; and increasing the time interval between said first and second clock signals, to thereby increase the short path limit of said data path, where the short path limit is the minimum allowable propagation time over said data path between said first and second devices.
Claim 10
Dependent Claim
17 words
A method as defined in claim 7, wherein said decreasing step comprises delaying said first clock signal.
Claim 11
Dependent Claim
36 words
A method as defined in claim 8, further comprising the step of monitoring errors in the data stored in said second device to determine the minimum acceptable time interval between said first and second clock signals.
Claim 12
Dependent Claim
20 words
A method as defined in claim 7, wherein said increasing step comprises the step of delaying said second clock signal.
Claim 13
Dependent Claim
36 words
A method as defined in claim 10, further comprising the step of monitoring errors in the data stored in said second device to determine the maximum acceptable time interval between said first and second clock signals.
Claim 14
Independent Claim
174 words
A method of testing a data processing system, said system being of the type having at least a first device providing a data output to a data path in response to a first clock signal and a second device for storing input data from said data path in response to a second clock signal, and means for providing said first and second clock signals to operate said system with a normal operating cycle, said method comprising the steps of: providing first and second clock signals with a cycle time longer than said normal operating cycle; stressing said data path in a first direction by delaying one of said first and second clock signals with respect to the other of said first and second clock signals; stressing said data path in a second direction by delaying the other of said first and second clock signals with respect to said one of said first and second clock signals; and thereafter providing said first and second clock signals to operate said system with said normal operating cycle.
Claim 15
Independent Claim
174 words
A method of testing a data processing system, said system being of the type having at least a first device providing a data output to a data path in response to a first clock signal and a second device for storing input data from said data path in response to a second clock signal, and means for providing said first and second clock signals to operate said system with a normal operating cycle, said method comprising the steps of: providing first and second clock signals with a cycle time longer than said normal operating cycle; stressing said data path in a first direction by delaying one of said first and second clock signals with respect to the other of said first and second clock signals; stressing said data path in a second direction by delaying the other of said first and second clock signals with respect to said one of said first and second clock signals; and thereafter providing said first and second clock signals to operate said system with said normal operating cycle.
Claim 16
Dependent Claim
24 words
A method of testing as defined in claim 12, wherein said one of said first and second clock signals is said first clock signal.
References Cited (Backward Citations)
US3047841A
Cited
US3196390A
Cited
US3252097A
Cited
US3633174A
Cited
US3659087A
Cited
US3814920A
Cited
US3805152A
Cited
US3737637A
Cited
US3784907A
Cited
US3783254A
Cited
US3761695A
Cited
US3916306A
Cited
US4058767A
Cited
US4025768A
Cited
US4063080A
Cited
US4063078A
Cited
US4144448A
Cited
US4298980A
Cited
US4476431A
Cited
US4362957A
Cited
US4477902A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-01-13 | 1989-07-15 | 1990-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-01-13 | 1993-07-15 | 1994-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-01-13 | 1997-07-15 | 1998-01-14 | $7700.00 | Window Closed / Lapsed |