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US3814920A Expired / Lapsed US ⏱️ 0.0 years remaining

Employing variable clock rate

Assignee: Wincor Nixdorf International GmbH
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Filing: 1972-02-15
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Granted: 1974-06-04
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Expires: 1992-02-15
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Abstract

Abstract A method and apparatus for fault diagnosis in pulse controlled devices whose control contains a logical network and a memory composed of a plurality of registers through the utilization of a data processing device wherein test apparatus is connected to the data processing device, the tested device internal timing pulse is switched off and replaced by a processing pulse supplied by the data processing device to form the basis on which the logical network of the test apparatus carries out a processing step, the contents of the test apparatus memory is transferred into the data processing device after each processing step carried out by the logical network of the test apparatus, the transferred information is compared with a standard in the data processing device in order to detect faults, and further wherein the contents of the memory registers can be changed by the data processing device before each processing step.

Inventors

  • 👤 H Huelters

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 00:35
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/267; G06F11/2294

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 167 words
An arrangement for diagnosing faults of a pulse-controlled device having a logical network for processing device data, a register having a plurality of stages and connected to said logical network, and a pulse generator for generating device control pulses connectable to said register, comprising: a data processing device for receiving device data including means for comparing the data with a standard, means for correcting erroneous data connected to said register and means connected to said pulse-controlled device for generating processing pulses and a plurality of control pulses; a first device connected between said data processing device and said pulse generator and said register for receiving processing pulses and a first of said control pulses and responsive thereto to disconnect said pulse generator from and connect the processing pulses to said register; and a second device connected between said register and said data processing device and operable in response to a second of said control signals to control the connection of said register stages as a ring-shift register.
Claim 2
Dependent Claim 167 words
An arrangement for diagnosing faults of a pulse-controlled device having a logical network for processing device data, a register having a plurality of stages and connected to said logical network, and a pulse generator for generating device control pulses connectable to said register, comprising: a data processing device for receiving device data including means for comparing the data with a standard, means for correcting erroneous data connected to said register and means connected to said pulse-controlled device for generating processing pulses and a plurality of control pulses; a first device connected between said data processing device and said pulse generator and said register for receiving processing pulses and a first of said control pulses and responsive thereto to disconnect said pulse generator from and connect the processing pulses to said register; and a second device connected between said register and said data processing device and operable in response to a second of said control signals to control the connection of said register stages as a ring-shift register.
Claim 3
Dependent Claim 63 words
The arrangement of claim 1, wherein said first device comprises a first AND circuit connected to said pulse generator, an inverter for receiving said first control signal connected to said first AND circuit, a second AND circuit connected to receive said processing pulses and said first control signal, and an OR circuit connected between said first and second AND circuits and said register.
Claim 4
Dependent Claim 85 words
The arrangement of claim 1, wherein said second device comprises a plurality of input circuits respectively connected to the stages of said register and operable in response to said second control signal to connect the associated stage with another stage to form a ring-shift register and disconnect the stages from said logical network, and a write circuit connected to a portion of said register stages and operable to write information in that portion of the register in response to a third of said control signals.
Claim 5
Dependent Claim 118 words
The arrangement of claim 3, wherein each of saiD register stages is a bistable circuit having a plurality of inputs ane outputs and each of said input circuits comprises a third and fourth AND circuits connected to receive data signals from said logical network, a second inverter connected to said third and fourth AND circuits for receiving and passing inverted thereto the second control signal, fifth and sixth AND circuits connected to receive said second control signal and connected to respective outputs of a preceeding bistable circuit, second and third OR circuits connected to said third and fifth AND circuits and to said fourth and sixth AND circuits, respectively, and to respective inputs of the associated bistable stage.
Claim 6
Dependent Claim 96 words
The arrangement of claim 4, wherein said write circuit comprises a pair of AND circuits each connected to receive said third control signal and respectively connected to said second and third OR circuits, a third inverter, one of said AND circuits connected to receive a write control signal from said data processing device and the other of said AND circuits connected to receive the inverted write control signal via said third inverter, and a fourth inverter connected to receive said third control signal and provide the inverted form thereof to said fifth and sixth AND circuits.

References Cited (Backward Citations)

US3387276A Cited
US3453601A Cited
US3588483A Cited
US3657527A Cited
US3673397A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-06-03 1977-12-03 1978-06-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-06-03 1981-12-03 1982-06-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-06-03 1985-12-03 1986-06-04 $7700.00 Window Closed / Lapsed

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