Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
167 words
An arrangement for diagnosing faults of a pulse-controlled device having a logical network for processing device data, a register having a plurality of stages and connected to said logical network, and a pulse generator for generating device control pulses connectable to said register, comprising: a data processing device for receiving device data including means for comparing the data with a standard, means for correcting erroneous data connected to said register and means connected to said pulse-controlled device for generating processing pulses and a plurality of control pulses; a first device connected between said data processing device and said pulse generator and said register for receiving processing pulses and a first of said control pulses and responsive thereto to disconnect said pulse generator from and connect the processing pulses to said register; and a second device connected between said register and said data processing device and operable in response to a second of said control signals to control the connection of said register stages as a ring-shift register.
Claim 2
Dependent Claim
167 words
An arrangement for diagnosing faults of a pulse-controlled device having a logical network for processing device data, a register having a plurality of stages and connected to said logical network, and a pulse generator for generating device control pulses connectable to said register, comprising: a data processing device for receiving device data including means for comparing the data with a standard, means for correcting erroneous data connected to said register and means connected to said pulse-controlled device for generating processing pulses and a plurality of control pulses; a first device connected between said data processing device and said pulse generator and said register for receiving processing pulses and a first of said control pulses and responsive thereto to disconnect said pulse generator from and connect the processing pulses to said register; and a second device connected between said register and said data processing device and operable in response to a second of said control signals to control the connection of said register stages as a ring-shift register.
Claim 3
Dependent Claim
63 words
The arrangement of claim 1, wherein said first device comprises a first AND circuit connected to said pulse generator, an inverter for receiving said first control signal connected to said first AND circuit, a second AND circuit connected to receive said processing pulses and said first control signal, and an OR circuit connected between said first and second AND circuits and said register.
Claim 4
Dependent Claim
85 words
The arrangement of claim 1, wherein said second device comprises a plurality of input circuits respectively connected to the stages of said register and operable in response to said second control signal to connect the associated stage with another stage to form a ring-shift register and disconnect the stages from said logical network, and a write circuit connected to a portion of said register stages and operable to write information in that portion of the register in response to a third of said control signals.
Claim 5
Dependent Claim
118 words
The arrangement of claim 3, wherein each of saiD register stages is a bistable circuit having a plurality of inputs ane outputs and each of said input circuits comprises a third and fourth AND circuits connected to receive data signals from said logical network, a second inverter connected to said third and fourth AND circuits for receiving and passing inverted thereto the second control signal, fifth and sixth AND circuits connected to receive said second control signal and connected to respective outputs of a preceeding bistable circuit, second and third OR circuits connected to said third and fifth AND circuits and to said fourth and sixth AND circuits, respectively, and to respective inputs of the associated bistable stage.
Claim 6
Dependent Claim
96 words
The arrangement of claim 4, wherein said write circuit comprises a pair of AND circuits each connected to receive said third control signal and respectively connected to said second and third OR circuits, a third inverter, one of said AND circuits connected to receive a write control signal from said data processing device and the other of said AND circuits connected to receive the inverted write control signal via said third inverter, and a fourth inverter connected to receive said third control signal and provide the inverted form thereof to said fifth and sixth AND circuits.