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Patent US4555842A successfully refreshed from Google Patents.
US4555842A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating VLSI CMOS devices having complementary threshold voltages
Assignee: Nokia Bell Labs
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Filing: 1984-03-19
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Granted: 1985-12-03
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Expires: 2004-03-19
Abstract
Abstract For optimal performance, the threshold voltages V TP and V TN of the p- and n-channel transistors in a CMOS device should be the respective complements of each other. In polysilicon-gate devices, this can be achieved by adjusting the corresponding gate-metal work function utilizing p + and n + polysilicon for the respective gates of the p- and n-channel transistors. However, when a refractory metal silicide-over-polysilicon gate structure is employed in a VLSI CMOS device in which the gates of a pair of adjacent complementary transistors are connected together, an anomalously large negative V TP is measured. The invention is a unique process sequence that achieves substantially complementary p- and n-channel transistor thresholds in a high-speed VLSI CMOS device that includes silicide-over-polysilicon gates.
Inventors
- 👤 Hyman J. Levinstein
- 👤 Sheila Vaidya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:51
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/663; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0177; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; Y; Y10; Y10S; Y10S148/00; Y10S148/082
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
79 words
A method of fabricating a CMOS device of the type that comprises substantially complementary-threshold-voltage NMOS and PMOS transistors which include silicide-on-doped polysilicon gates, said method comprising the steps of forming a polysilicon layer on a substrate, introducing p-type dopants only into regions of said layer from which PMOS-transistor gates are to be formed, driving substantially all of said dopants into lattice sites in said regions of said layer, and subsequently forming a silicide precursor layer on said polysilicon layer.
Claim 2
Independent Claim
79 words
A method of fabricating a CMOS device of the type that comprises substantially complementary-threshold-voltage NMOS and PMOS transistors which include silicide-on-doped polysilicon gates, said method comprising the steps of forming a polysilicon layer on a substrate, introducing p-type dopants only into regions of said layer from which PMOS-transistor gates are to be formed, driving substantially all of said dopants into lattice sites in said regions of said layer, and subsequently forming a silicide precursor layer on said polysilicon layer.
Claim 3
Dependent Claim
32 words
A method as in claim 1 further including the steps of etching said precursor and polysilicon layers to define composite gates, and sintering said device to convert said precursor layer to silicide.
Claim 4
Dependent Claim
56 words
A method as in claim 2 including the further steps of introducing n-type dopants only into NMOS source and drain regions of said substrate and into the silicide portions of the NMOS gates, and introducing p-type dopants only into PMOS source and drain regions of said substrate and into the silicide portions of the PMOS gates.
Claim 5
Dependent Claim
48 words
A method as in claim 3 including the further step of annealing said device to activate dopants in said source and drain regions and to redistribute dopant from the silicide portions of the NMOS gates into the underlying polysilicon portions to enhance the conductivity of said polysilicon portions.
Claim 6
Dependent Claim
56 words
A method as in claim 4 wherein the concentration of n-type dopant and the temperatures employed during fabrication of said device are selected to achieve a relatively low level of redistribution of n-type dopant from the polysilicon portions of the NMOS gates into the overlying silicide portions and to the polysilicon portions of the PMOS gates.
Claim 7
Dependent Claim
43 words
A method as in claim 5 wherein said driving step comprises forming a cap layer on said doped polysilicon layer, and heating said device with said cap layer in place to drive dopants into lattice sites in the specified regions of said layer.
Claim 8
Dependent Claim
20 words
A method as in claim 5 wherein said driving step comprises rapid thermal annealing of said device utilizing a laser.
Claim 9
Independent Claim
105 words
A method of fabricating a CMOS device of the type that comprises substantially complementary-threshold-voltage NMOS and PMOS transistors which include silicide-on-doped polysilicon gates, said method comprising the steps of forming a polysilicon layer on a substrate, introducing p-type dopants only into regions of said polysilicon layer from which PMOS-transistor gates are to be formed, introducing n-type dopants only into regions of said polysilicon layer from which NMOS-transistor gates are to be formed, forming a cap layer on said doped polysilicon layer, and heating said device with said cap layer in place to drive dopants into lattice sites in the specified regions of said polysilicon layer.
Claim 10
Independent Claim
105 words
A method of fabricating a CMOS device of the type that comprises substantially complementary-threshold-voltage NMOS and PMOS transistors which include silicide-on-doped polysilicon gates, said method comprising the steps of forming a polysilicon layer on a substrate, introducing p-type dopants only into regions of said polysilicon layer from which PMOS-transistor gates are to be formed, introducing n-type dopants only into regions of said polysilicon layer from which NMOS-transistor gates are to be formed, forming a cap layer on said doped polysilicon layer, and heating said device with said cap layer in place to drive dopants into lattice sites in the specified regions of said polysilicon layer.
Claim 11
Dependent Claim
58 words
A method as in claim 8 further including the steps of after said heating step, removing the cap layer from said polysilicon layer, forming a silicide precursor layer on said doped polysilicon layer, etching said precursor and polysilicon layers to define composite gates, and sintering said device to convert the remaining portions of said precursor layer to silicide.
Claim 12
Dependent Claim
55 words
A method as in claim 9 including the further steps of introducing n-type dopants only into NMOS source and drain regions of said substrate and into the silicide portions of the NMOS gates, and introducing p-type dopants only into source and drain regions of said substrate and into the silicide portions of the PMOS gates.
Claim 13
Dependent Claim
45 words
A method as in claim 10 including the further step of annealing said device to activate dopants in said source and drain regions and to redistribute dopant from the silicide portions of the NMOS gates into the underlying gate polysilicon to enhance the conductivity thereof.
Claim 14
Dependent Claim
21 words
A method as in claim 11 wherein said annealing step is carried out at a temperature of approximately 900 degrees Celsius.
Claim 15
Dependent Claim
13 words
A method as in claim 12 wherein said cap layer comprises silcon dioxide.
Claim 16
Dependent Claim
21 words
A method as in claim 13 wherein said p-type dopants are selected from the group consisting of boron and boron difluoride.
Claim 17
Dependent Claim
12 words
A method as in claim 14 wherein said n-type dopants comprise arsenic.
Claim 18
Dependent Claim
13 words
A method as in claim 15 wherein said silicide layer comprises tantalum silicide.
Claim 19
Dependent Claim
29 words
A method as in claim 8 wherein said dopant introducing step comprises introducing dopants only into regions of said polysilicon layer from which PMOS-transistor gates are to be formed.
Claim 20
Dependent Claim
58 words
A method as in claim 17 further including the steps of after said heating step, removing the cap layer from said polysilicon layer, forming a silicide precursor layer on said doped polysilicon layer, etching said precursor and polysilicon layers to define composite gates, and sintering said device to convert the remaining portions of said precursor layer to silicide.
Claim 21
Dependent Claim
56 words
A method as in claim 18 including the further steps of introducing n-type dopants only into NMOS source and drain regions of said substrate and into the silicide portions of the NMOS gates, and introducing p-type dopants only into PMOS source and drain regions of said substrate and into the silicide portions of the PMOS gates.
Claim 22
Dependent Claim
48 words
A method as in claim 19 including the further step of annealing said device to activate dopants in said source and drain regions and to drive dopant from the silicide portions of the NMOS gates into the underlying priorly undoped gate polysilicon to render said polysilicon electrically conductive.
Claim 23
Dependent Claim
21 words
A method as in claim 20 wherein said annealing step is carried out at a temperature of approximately 900 degrees Celsius.
Claim 24
Dependent Claim
13 words
A method as in claim 21 wherein said cap layer comprises silicon dioxide.
Claim 25
Dependent Claim
21 words
A method as in claim 22 wherein said p-type dopants are selected from the group consisting of boron and boron difluoride.
Claim 26
Dependent Claim
12 words
A method as in claim 23 wherein said n-type dopants comprise arsenic.
Claim 27
Dependent Claim
13 words
A method as in claim 24 wherein said silicide layer comprises tantalum silicide.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-12-02 | 1989-06-03 | 1989-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-12-02 | 1993-06-03 | 1993-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-12-02 | 1997-06-03 | 1997-12-03 | $7700.00 | Window Closed / Lapsed |