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US4403392A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing a semiconductor device

Assignee: Toshiba Corp
•
Filing: 1980-05-22
•
Granted: 1983-09-13
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Expires: 2000-05-22
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Abstract

Abstract A method for manufacturing a semiconductor device having a high breakdown voltage and a high reliability, comprises (a) forming on a semiconductor substrate an insulating layer having a diffusion window; (b) forming an impurity-doped poly-silicon layer on the insulating layer and on that portion of the semiconductor substrate which is exposed through the diffusion window; (c) forming an undoped poly-silicon layer on the impurity-doped poly-silicon layer; (d) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer and undoped poly-silicon layer, thus diffusing the impurity from the impurity-doped poly-silicon layer into the semiconductor substrate through the diffusion window and converting the undoped poly-silicon layer to a silicon oxide layer; (e) forming on the silicon oxide layer an oxidation-resisting mask layer in a desired pattern; and (f) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer, silicon oxide layer and mask layer, thus converting those portions of the impurity-doped poly-silicon layer which lie beneath those portions of the silicon oxide layer which are exposed through the mask layer to impurity-doped silicon oxide layers, whereby the remaining portions of the impurity-doped poly-silicon layer provide an interconnection electrode layer having a desired pattern.

Inventors

  • 👤 Jiro Oshima
  • 👤 Masaharu Aoyama
  • 👤 Seiji Yasuda
  • 👤 Toshio Yonezawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 19:27
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/44; H10W20/4451; H10D; H10D64/00; H10D64/01; H10D64/011; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; H10P95/00; H10W20/42; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/92

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 188 words
A method for manufacturing a semiconductor device comprising: (a) forming on a semiconductor substrate an insulating layer having a diffusion window; (b) forming an impurity-doped poly-silicon layer on the insulating layer and on that portion of the semiconductor substrate which is exposed through the diffusion window, said impurity being arsenic; (c) forming an undoped poly-silicon layer on the impurity-doped poly-silicon layer; (d) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer and undoped poly-silicon layer, thus diffusing the impurity from the impurity-doped poly-silicon layer into the semiconductor substrate through the diffusion window and converting the undoped poly-silicon layer to a silicon oxide layer; (e) forming on the silicon oxide layer an oxidation-resisting mask layer in a desired pattern; and (f) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer, silicon oxide layer and mask layer, thus converting those portions of the impurity-doped poly-silicon layer which lie beneath those portions of the silicon oxide layer which are exposed through the mask layer to impurity-doped silicon oxide layers, whereby the remaining portions of the impurity-doped poly-silicon layer provide an interconnection electrode layer having a desired pattern.
Claim 2
Independent Claim 188 words
A method for manufacturing a semiconductor device comprising: (a) forming on a semiconductor substrate an insulating layer having a diffusion window; (b) forming an impurity-doped poly-silicon layer on the insulating layer and on that portion of the semiconductor substrate which is exposed through the diffusion window, said impurity being arsenic; (c) forming an undoped poly-silicon layer on the impurity-doped poly-silicon layer; (d) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer and undoped poly-silicon layer, thus diffusing the impurity from the impurity-doped poly-silicon layer into the semiconductor substrate through the diffusion window and converting the undoped poly-silicon layer to a silicon oxide layer; (e) forming on the silicon oxide layer an oxidation-resisting mask layer in a desired pattern; and (f) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer, silicon oxide layer and mask layer, thus converting those portions of the impurity-doped poly-silicon layer which lie beneath those portions of the silicon oxide layer which are exposed through the mask layer to impurity-doped silicon oxide layers, whereby the remaining portions of the impurity-doped poly-silicon layer provide an interconnection electrode layer having a desired pattern.
Claim 3
Dependent Claim 17 words
A method according to claim 1, wherein said undoped poly-silicon layer is 500 to 1,000 A thick.
Claim 4
Dependent Claim 42 words
A method according to claim 1 wherein the impurity concentration of said undoped silicon oxide layer is 1×10 17 cm -3 or less and that of said impurity-doped silicon oxide layer is 1×10 18 cm -3 to 1×10 22 cm -3 .
Claim 5
Dependent Claim 16 words
A method according to claim 1, wherein said oxidation-resisting mask layer is made of silicon nitride.
Claim 6
Dependent Claim 42 words
A method according to claim 1, further comprising steps of removing said oxidation-resisting mask layer, forming a contact hole in the silicon oxide layer laid on said interconnection electrode layer, and forming a metal electrode in a region including said contact hole.
Claim 7
Dependent Claim 17 words
A method according to claim 1 wherein said impurity-doped poly-silicon layer is formed by chemical vapor deposition.
Claim 8
Dependent Claim 15 words
A method according to claim 1 wherein said impurity-doped poly-silicon layer is formed by sputtering.
Claim 9
Dependent Claim 22 words
A method according to claim 1 wherein said impurity-doped poly-silicon layer is formed by impurity ion implantation into an undoped poly-silicon layer.

References Cited (Backward Citations)

US4074304A Cited
US4124934A Cited
US4143178A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1986-09-12 1987-03-14 1987-09-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1990-09-12 1991-03-14 1991-09-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1994-09-12 1995-03-14 1995-09-13 $7700.00 Window Closed / Lapsed

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