Propagation delay generator

Claim 2

A propagation delay generator circuit having a first voltage conductor, a second voltage conductor, an input conductor responsive to an input signal having a first and a second level, and an output conductor, for generating a delayed digital output signal responsive to said input signal, comprising: input means coupled to said first voltage conductor, said second voltage conductor, said input conductor, and a first node, and responsive to said input signal for initializing a charging signal having a first voltage level at said first node when said input signal is at said first level; capacitive means coupled to said first voltage conductor, said second voltage conductor, said first node, and a second node, and responsive to said charging signal for charging said first node to a second voltage level when said input signal is at said second level and for providing a gating signal having a third voltage level at said second node subsequent to receiving said charging signal; said capacitive means comprising: a current source coupled between said first voltage conductor and said first node; a resistor coupled between said first node and said second node; and a capacitor coupled between said second voltage conductor and said second node; voltage level means coupled between said first node and said second voltage conductor for establishing said second voltage level at said first node; and output means coupled to said first voltage conductor, said second voltage conductor, and said second node, and responsive to said gating signal for providing said output signal.

Claim 3

The circuit according to claim 1 wherein said input means comprises: a first transistor having a base, collector, and emitter, said base coupled to said input conductor, said collector coupled to said first voltage conductor, said emitter coupled to said second voltage conductor; a second transistor having a base, collector, and emitter, said collector and base coupled together and to said base of said first transistor; and a third transistor having a base, collector, and emitter, said base coupled to said emitter of said first transistor, said emitter coupled to said second voltage conductor, said collector coupled to both said emitter of said second transistor and said first node.

Claim 4

The circuit according to claim 1 wherein said output means comprises: a fourth transistor having a base, collector, and emitter, said base coupled to said second node, said collector coupled to said first voltage conductor; a fifth transistor having a base, collector, and emitter, said collector and base coupled together and to said base of said fourth transistor; and a sixth transistor having a base, collector, and emitter, said base coupled to said emitter of said fourth transistor, said emitter coupled to said second voltage conductor, said collector coupled to said emitter of said fifth transistor and said first voltage conductor, said collector providing said output signal.

Claim 5

The circuit according to claim 1 wherein said voltage level means comprises a plurality of diode connected transistors coupled in series between said first node and said second voltage conductor.

Claim 6

The circuit according to claim 1 wherein said voltage level means comprises an NV BE network.

Claim 7

A propagation delay generator in a bubble memory system further having a control amplifier and a ramp generator, said control amplifier initiating a bubble generate waveform and an input signal having a first and a second level, said propagation delay generator having a first voltage conductor, a second voltage conductor, an input conductor responsive to said input signal, and an output conductor providing an output signal to said ramp generator, wherein the rise time of said bubble generate waveform is controlled by said control amplifier, said propagation delay generator controls the duration of said bubble generate waveform with a magnitude above a specific percentage of peak amplitude, said ramp generator controlling said bubble generate waveform fall time, said propagation delay generator comprising: input means coupled to said first voltage conductor, said second voltage conductor, said input conductor, and a first node, and responsive to said input signal for initializing a charging signal having a first voltage level at said first node when said input signal is at said first level; capacitive means coupled to said first voltage conductor, said second voltage conductor, said first node, and a second node, and responsive to said charging signal for charging said first node to a second voltage level when said input signal is at said second level and for providing a gating signal having a third voltage level at said second node subsequent to receiving said charging signal; said capacitive means comprising: a resistor coupled between said first node and said second node; and a capacitor coupled between said second voltage conductor and said second node; and output means coupled to said first voltage conductor, said second voltage conductor, and said second node and responsive to said gating signal for providing said output signal, wherein the bubble generate waveform is maintained at a magnitude above a specified percentage of peak amplitude during the time between said input signal and said output signal.

Claim 8

A propagation delay generator in a bubble memory system further having a control amplifier and a ramp generator, said control amplifier initiating a bubble generate waveform and an input signal having a first and a second level, said propagation delay generator having a first voltage conductor, a second voltage conductor, an input conductor responsive to said input signal, and an output conductor providing an output signal to said ramp generator, wherein the rise time of said bubble generate waveform is controlled by said control amplifier, said propagation delay generator controls the duration of said bubble generate waveform with a magnitude above a specific percentage of peak amplitude, said ramp generator controlling said bubble generate waveform fall time, said propagation delay generator comprising: input means coupled to said first voltage conductor, said second voltage conductor, said input conductor, and a first node, and responsive to said input signal for initializing a charging signal having a first voltage level at said first node when said input signal is at said first level; capacitive means coupled to said first voltage conductor, said second voltage conductor, said first node, and a second node, and responsive to said charging signal for charging said first node to a second voltage level when said input signal is at said second level and for providing a gating signal having a third voltage level at said second node subsequent to receiving said charging signal; said capacitive means comprising: a resistor coupled between said first node and said second node; and a capacitor coupled between said second voltage conductor and said second node; and output means coupled to said first voltage conductor, said second voltage conductor, and said second node and responsive to said gating signal for providing said output signal, wherein the bubble generate waveform is maintained at a magnitude above a specified percentage of peak amplitude during the time between said input signal and said output signal.