Programmable proportional clock edge delay circuit

Claim 2

In combination, a clock edge delay circuit for delaying the clock edges of input clock pulses supplied by a clock pulse source comprising: a ramp generator including a constant current source for generating linear ramp voltages; ramp generator control means responsive to successive clock pulse edges for alternately initiating and terminating said ramp voltage generation; reference voltage means including a digital-to-analog converter for providing any selected one of a plurality of discrete reference voltages; and a voltage comparator having a first input, a second input and an output, said first input being coupled to said ramp voltage generator, said second input being coupled to said reference voltage means and providing delayed clock pulse edges at said output responsive to voltage comparisons on said input; whereby, when said ramp voltage bears a predetermined relation to said selected discrete reference voltage, said circuit at said voltage comparator output provides delayed clock edges delayed in time from said input clock pulse edges by a preselected amount proportional to said selected reference voltage.

Claim 3

A clock edge delay circuit in accordance with claim 1 wherein said first comparator input is a negative input and wherein said second comparator input is a positive input to thereby cause said delayed clock edges to be negative going.

Claim 4

A clock edge delay circuit in accordance with claim 1 wherein said first comparator input is a positive input and wherein said second comparator input is a negative input to thereby cause said delayed clock edges to be positive going.

Claim 5

A clock edge delay circuit in accordance with claim 1 where said ramp generator control means comprises an open collector inverter.

Claim 6

A clock edge delay circuit in accordance with claim 1 wherein said digital-to-analog converter has a plurality of digital inputs to provide selection of any one of said plurality of discrete reference vOltages in response to the digital input conditions at said inputs.

Claim 7

A clock edge delay circuit in accordance with claim 1 wherein said digital-to-analog converter produces discrete current outputs and wherein said reference voltage means additionally includes an operational amplifier to convert said discrete current outputs of said digital-to-analog converter to said discrete reference voltages.

Claim 8

A clock edge delay circuit in accordance with claim 1 wherein said ramp generator additionally includes a capacitor coupled to said constant current source for being charged by said constant current source to produce said linear ramp voltages.

Claim 9

A clock edge delay circuit in accordance with claim 7 wherein said constant current source comprises first and second transistors having their bases mutually coupled and wherein the collector of said first transistor is coupled to said capacitor.

Claim 10

In combination, a clock edge delay circuit for delaying the clock edges of input clock pulses supplied by a clock pulse source comprising: a ramp generator including a constant current source and a capacitor, said capacitor being coupled to said constant current source for being charged by said constant current source for generating linear ramp voltages; ramp generator control means including an open collector inverter responsive to successive input clock pulse edges for controlling the charging and discharging of said capacitor to alternately initiate and terminate said ramp voltage generation; reference voltage means including a digital-to-analog converter and an operational amplifier, said digital-to-analog converter having a plurality of digital inputs and providing any one of a plurality of discrete current outputs in response to the digital input conditions at said inputs, said operational amplifier being coupled to said digital-to-analog converter for converting said discrete current outputs to discrete reference voltages, said digital-to-analog converter and said operational amplifier combining to provide any selected one of a plurality of said discrete reference voltages; and a voltage comparator having a first input, a second input and an output, said first input being coupled to said ramp voltage generator, said second input being coupled to said reference voltage means and providing delayed clock pulse edges at said output responsive to voltage comparisons on said input terminals; whereby, when said ramp voltage bears a predetermined relation to said selected discrete reference voltage, said circuit at said voltage comparator output provides delayed clock edges delayed in time from said input clock pulse edges by a preselected amount proportional to said selected discrete reference voltage.

Claim 11

In combination, a clock edge delay circuit for delaying the clock edges of input clock pulses supplied by a clock pulse source comprising: a ramp generator including a constant current source and a capacitor, said capacitor being coupled to said constant current source for being charged by said constant current source for generating linear ramp voltages; ramp generator control means including an open collector inverter responsive to successive input clock pulse edges for controlling the charging and discharging of said capacitor to alternately initiate and terminate said ramp voltage generation; reference voltage means including a digital-to-analog converter and an operational amplifier, said digital-to-analog converter having a plurality of digital inputs and providing any one of a plurality of discrete current outputs in response to the digital input conditions at said inputs, said operational amplifier being coupled to said digital-to-analog converter for converting said discrete current outputs to discrete reference voltages, said digital-to-analog converter and said operational amplifier combining to provide any selected one of a plurality of said discrete reference voltages; and a voltage comparator having a first input, a second input and an output, said first input being coupled to said ramp voltage generator, said second input being coupled to said reference voltage means and providing delayed clock pulse edges at said output responsive to voltage comparisons on said input terminals; whereby, when said ramp voltage bears a predetermined relation to said selected discrete reference voltage, said circuit at said voltage comparator output provides delayed clock edges delayed in time from said input clock pulse edges by a preselected amount proportional to said selected discrete reference voltage.