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US3731206A Expired / Lapsed US ⏱️ 0.0 years remaining

Multiplying circuit with pulse duration control means

Assignee: Xerox Corp
•
Filing: 1970-10-14
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Granted: 1973-05-01
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Expires: 1990-10-14
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Abstract

Abstract A multiplying circuit wherein a capacitor is charged at a constant rate for the duration of an input pulse and then discharged at another constant rate. The total of the charge and discharge times is a predetermined multiple of the input pulse duration. A pulse generator supplies an output pulse having a duration equal to the sum of the capacitor charge and discharge times.

Inventors

  • 👤 J Veale

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 11:03
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/32; H04N1/36; G; G06; G06G; G06G7/00; G06G7/12; G06G7/16; G06G7/161; H02; H02P; H02P5/00; H02P5/46; H02P5/52

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 241 words
A multiplying circuit comprising a pulse generator, having input and output terminals, for generating an electrical signal, T3, at said output terminal when a voltage above a reference voltage level is at said input terminal, a capacitor, having first and second terminals, coupled to said input terminal of said generating means at said first terminal and to said reference voltage level at said second terminal, a diode, having anode and cathode electrodes, coupled to said capacitor first terminal at said cathode electrode and to said reference voltage level at said anode electrode, said diode preventing said capacitor from being charged to a voltage below said reference voltage level, a first constant current source having an output current I1, a second constant current source having an output current I2 coupled to said capacitor first terminal, and switching means, having input, output and switching terminals, coupled to said first current source at said input terminal and to said capacitor first terminal at said output terminal, to apply said current I1 to said capacitor when an electrical pulse signal T1 is at said switching terminal, said capacitor being charged by current I3 I1-I2 for the duration of pulse T1 and thereafter by current I2, the voltage on said capacitor, when a potential above said reference voltage level, causing the generation of pulse T3 at the output of said pulse generating means, the relation between pulse T3 and T1 being substantially T3 (I1 . T1)/I2
Claim 2
Dependent Claim 241 words
A multiplying circuit comprising a pulse generator, having input and output terminals, for generating an electrical signal, T3, at said output terminal when a voltage above a reference voltage level is at said input terminal, a capacitor, having first and second terminals, coupled to said input terminal of said generating means at said first terminal and to said reference voltage level at said second terminal, a diode, having anode and cathode electrodes, coupled to said capacitor first terminal at said cathode electrode and to said reference voltage level at said anode electrode, said diode preventing said capacitor from being charged to a voltage below said reference voltage level, a first constant current source having an output current I1, a second constant current source having an output current I2 coupled to said capacitor first terminal, and switching means, having input, output and switching terminals, coupled to said first current source at said input terminal and to said capacitor first terminal at said output terminal, to apply said current I1 to said capacitor when an electrical pulse signal T1 is at said switching terminal, said capacitor being charged by current I3 I1-I2 for the duration of pulse T1 and thereafter by current I2, the voltage on said capacitor, when a potential above said reference voltage level, causing the generation of pulse T3 at the output of said pulse generating means, the relation between pulse T3 and T1 being substantially T3 (I1 . T1)/I2
Claim 3
Dependent Claim 21 words
A multiplying circuit according to claim 1 further including means to limit the voltage on said capacitor to a maximum value.

References Cited (Backward Citations)

US2995710A Cited
US3094667A Cited
US3205448A Cited
US2987633A Cited
US3053996A Cited
US3214696A Cited
US3346743A Cited
US3473050A Cited
US3571626A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-04-30 1976-10-30 1977-05-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-04-30 1980-10-30 1981-05-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-04-30 1984-10-30 1985-05-01 $7700.00 Window Closed / Lapsed

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