US3175101A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse generating circuits which provide for rapid recovery of the delay line timing element
Assignee: AT&T Inc
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Filing: 1962-06-29
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Granted: 1965-03-23
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Expires: 1982-06-29
Abstract
No abstract record available.
Inventors
- 👤 Gilbert A Van Dine
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:49
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/284; H03K5/00; H03K5/01; H03K5/04; H03K5/06
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
125 words
A PULSE GENERATOR COMPRISING A TRANSISTOR HAVING AN INPUT ELECTRODE, AN OUTPUT ELECTRODE AND A COMMON ELECTRODE, MEANS FOR CONNECTING SAID COMMON ELECTRODE TO A REFERENCE POTENTIAL, MEANS FOR NORMALLY BIASING SAID TRANSISTOR INTO CONDUCTION, A DELAY LINE HAVING ONE END CONNECTED TO SAID INPUT ELECTRODE, INPUT MEANS FOR DELIVERING PULSES OF A DURATION OF AT LEAST TWICE THE ONEWAY PROPAGATION TIME OF SAID DELAY LINE, SAID DELAY LINE HAVING ITS COMMON TERMINAL CONNECTED TO SAID INPUT MEANS, AND A DIODE HAVING ONE TERMINAL CONNECTED TO THE OTHER END OF SAID DELAY LINE WITH THE OTHER TERMINAL THEREOF CONNECTED TO A REFERENCE POTENTIAL, THE POLING OF SAID DIODE WITH RESPECT TO SAID DELAY LINE BEING THE SAME AS THE INPUT-COMMON ELECTRODE PATH OF SAID TRANSISTOR.
Claim 2
Dependent Claim
125 words
A PULSE GENERATOR COMPRISING A TRANSISTOR HAVING AN INPUT ELECTRODE, AN OUTPUT ELECTRODE AND A COMMON ELECTRODE, MEANS FOR CONNECTING SAID COMMON ELECTRODE TO A REFERENCE POTENTIAL, MEANS FOR NORMALLY BIASING SAID TRANSISTOR INTO CONDUCTION, A DELAY LINE HAVING ONE END CONNECTED TO SAID INPUT ELECTRODE, INPUT MEANS FOR DELIVERING PULSES OF A DURATION OF AT LEAST TWICE THE ONEWAY PROPAGATION TIME OF SAID DELAY LINE, SAID DELAY LINE HAVING ITS COMMON TERMINAL CONNECTED TO SAID INPUT MEANS, AND A DIODE HAVING ONE TERMINAL CONNECTED TO THE OTHER END OF SAID DELAY LINE WITH THE OTHER TERMINAL THEREOF CONNECTED TO A REFERENCE POTENTIAL, THE POLING OF SAID DIODE WITH RESPECT TO SAID DELAY LINE BEING THE SAME AS THE INPUT-COMMON ELECTRODE PATH OF SAID TRANSISTOR.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1968-03-22 | 1968-09-21 | 1969-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1972-03-22 | 1972-09-21 | 1973-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1976-03-22 | 1976-09-21 | 1977-03-23 | $7700.00 | Window Closed / Lapsed |