Monolithically integrated semiconductor circuit with transistors

Claim 2

Monolithically integrated semiconductor circuit having elements formed on the front side of a monocrystalline semiconductor chip, the semiconductor chip having a first and a second electric terminal addressable by a respective supply potential, the first terminal carrying the supply potential for the integrated circuit, and the second terminal carrying a substrate bias supply potential applied to a substrate region bordering on the rear side of the semiconductor chip, both of the supply potentials being delivered by a d-c power source, the semiconductor circuit proper having an input addressable by a reference potential, comprising a voltage divider bridging both of the supply terminals and exclusively providing the reference potential, said voltage divider having a first part connected to the first terminal delivering the supply potential for the integrated circuit, said first part being the semiconductor circuit proper to which the reference voltage is applicable, and a second part connected to the second terminal delivering the substrate bias supply potential and generating the reference potential as well as the substrate bias supply potential, said second part having means for delivering to the semiconductor circuit proper said reference potential at a constant value and independently of the respective operating state of the semiconductor circuit proper, the semiconductor circuit proper being directly connected to an output of said second part and including a source of another reference potential, and wherein said semiconductor circuit proper has an internal terminal for applying a supply potential differing from said reference potential, said internal terminal being directly connected to said first terminal of the semiconductor chip, said second part including a substrate bias generator having a substrate terminal identical with a further supply terminal for carrying said other reference potential, said further supply terminal identical with said substrate terminal being directly connected to said second supply terminal of the semiconductor chip and wherein said substrate bias generator comprises an operational amplifier with negative feedback having an output and a non-inverting and an inverting input, said output of said operational amplifier being directly connected to said inverting input thereof as well as to an internal supply input carrying said first-mentioned reference potential for the semiconductor circuit proper, said internal supply input being connected via a resistance to said substrate terminal simultaneously carrying said other reference potential for said substrate bias generator.

Claim 3

Integrated semiconductor circuit according to claim 1 wherein said inverting input of said operational amplifier is connected to a null potential derivable from the supply potential present at said supply terminals of the semiconductor chip by means of a voltage divider connected across said last-mentioned supply terminals.

Claim 4

Integrated semiconductor circuit according to claim 1 wherein said substrate bias generator and said semiconductor circuit proper comprise MOS field-effect transistors of the same channel type.

Claim 5

Integrated semiconductor circuit according to claim 3 wherein said channel type is an n-channel type.

Claim 6

Monolithically integrated semiconductor circuit having elements formed on the front side of a monocrystalline semiconductor chip, the semiconductor chip having a first and a second electric terminal addressable by a respective supply potential, the first terminal carrying the supply potential for the integrated circuit, and the second terminal carrying a substrate bias supply potential applied to a substrate region bordering on the rear side of the semiconductor chip, both of the supply potentials being delivered by a d-c power source, the semiconductor circuit proper having an input addressable by a reference potential, comprising a voltage divider bridging both of the supply terminals and exclusively providing the reference potential, said voltage divider having a first part connected to the first terminal delivering the supply potential for the integrated circuit, said first part being the semiconductor circuit proper to which the reference voltage is applicable, and a second part connected to the second terminal delivering the substrate bias supply potential and generating the reference potential as well as the substrate bias supply potential, said second part having means for delivering to the semiconductor circuit proper said reference potential at a constant value and independently of the respective operating state of the semiconductor circuit proper, the semiconductor circuit proper being directly connected to an output of said second part; further including a source of another reference potential, and wherein said semiconductor circuit proper has an internal terminal for applying a supply potential differing from said reference potential, said internal terminal being directly connected to said first terminal of the semiconductor chip, said second part including a substrate bias generator having a substrate terminal identical with a further supply terminal for carrying said other reference potential, said further supply terminal identical with said substrate terminal being directly connected to said second supply terminal of the semiconductor chip; and wherein said substrate bias generator comprises an amplifier formed of a plurality of cascaded inverters, and including a series circuit between said two supply terminals of the semiconductor chip, said series circuit being formed by said series connection of said substrate bias generator and the semiconductor circuit proper and being bridged by each of the cascaded inverters following the first of said cascaded inverters, said substrate bias generator comprising a field-effect transistor, and the semiconductor circuit proper comprising field-effect transistors, all of said field-effect transistors being of one channel type, said series connection being of said field-effect transistor of said substrate bias generator and current supply paths of the semiconductor circuit proper, each of said following cascaded inverters comprising an MOS driver transistor and a load transistor connected as a diode, said driver transistor having a source terminal connected to said substrate terminal and a drain connected to said one of the two supply terminals of the semiconductor chip simultaneously connected directly to the semiconductor circuit proper, said driver transistors having gates, the gates of the driver transistors of the following cascaded inverters being connected to the respective drain of the driver transistor of the respective preceding cascaded inverter, and the gate of the driver transistor of the first cascaded inverter being connected to the drain of the driver transistor of the last cascaded inverter, said driver transistors and said load transistors being of the same channel type as that of the field-effect transistors of the semiconductor circuit proper; and wherein the semiconductor circuit proper comprises MOS transistors and is controlled via a control input by a circuit part, said control input being connected to the gate of an input driver transistor, said input driver transistor having a source terminal connected to said substrate terminal and a drain terminal connected via the source-drain path of a load transistor to said first one of the two supply terminals of the semiconductor chip connected to the semiconductor circuit proper, said drain terminal being further connected to the gate of a transistor forming the input of the semiconductor circuit proper and, in turn, connected by the source terminal thereof to the output of said substrate bias generator.

Claim 7

Monolithically integrated semiconductor circuit having elements formed on the front side of a monocrystalline semiconductor chip, the semiconductor chip having a first and a second electric terminal addressable by a respective supply potential, the first terminal carrying the supply potential for the integrated circuit, and the second terminal carrying a substrate bias supply potential applied to a substrate region bordering on the rear side of the semiconductor chip, both of the supply potentials being delivered by a d-c power source, the semiconductor circuit proper having an input addressable by a reference potential, comprising a voltage divider bridging both of the supply terminals and exclusively providing the reference potential, said voltage divider having a first part connected to the first terminal delivering the supply potential for the integrated circuit, said first part being the semiconductor circuit proper to which the reference voltage is applicable, and a second part connected to the second terminal delivering the substrate bias supply potential and generating the reference potential as well as the substrate bias supply potential, said second part having means for delivering to the semiconductor circuit proper said reference potential at a constant value and independently of the respective operating state of the semiconductor circuit proper, the semiconductor circuit proper being directly connected to an output of said second part; further including a source of another reference potential, and wherein said semiconductor circuit proper has an internal terminal for applying a supply potential differing from said reference potential, said internal terminal being directly connected to said first terminal of the semiconductor chip, said second part including a substrate bias generator having a substrate terminal identical with a further supply terminal for carrying said other reference potential, said further supply terminal identical with said substrate terminal being directly connected to said second supply terminal of the semiconductor chip; and wherein said substrate bias generator comprises an amplifier formed of a plurality of cascaded inverters, and including a series circuit between said two supply terminals of the semiconductor chip, said series circuit being formed by said series connection of said substrate bias generator and the semiconductor circuit proper and being bridged by each of the cascaded inverters following the first of said cascaded inverters, said substrate bias generator comprising a field-effect transistor, and the semiconductor circuit proper comprising field-effect transistors, all of said field-effect transistors being of one channel type, said series connection being of said field-effect transistor of said substrate bias generator and current supply paths of the semiconductor circuit proper, each of said following cascaded inverters comprising an MOS driver transistor and a load transistor connected as a diode, said driver transistor having a source terminal connected to said substrate terminal and a drain connected to said one of the two supply terminals of the semiconductor chip simultaneously connected directly to the semiconductor circuit proper, said driver transistors having gates, the gates of the driver transistors of the following cascaded inverters being connected to the respective drain of the driver transistor of the respective preceding cascaded inverter, and the gate of the driver transistor of the first cascaded inverter being connected to the drain of the driver transistor of the last cascaded inverter, said driver transistors and said load transistors being of the same channel type as that of the field-effect transistors of the semiconductor circuit proper; and wherein the semiconductor circuit proper comprises MOS transistors and is controlled via a control input by a circuit part, said control input being connected to the gate of an input driver transistor, said input driver transistor having a source terminal connected to said substrate terminal and a drain terminal connected via the source-drain path of a load transistor to said first one of the two supply terminals of the semiconductor chip connected to the semiconductor circuit proper, said drain terminal being further connected to the gate of a transistor forming the input of the semiconductor circuit proper and, in turn, connected by the source terminal thereof to the output of said substrate bias generator.

Claim 8

Monolithically integrated semiconductor circuit having elements formed on the front side of a monocrystalline semiconductor chip, the semiconductor chip having a first and a second electric terminal addressable by a respective supply potential, the first terminal carrying the supply potential for the integrated circuit, and a second terminal carrying a substrate bias supply potential applied to a substrate region bordering on the rear side of the semiconductor chip, both of the supply potentials being delivered by a d-c power source, the semiconductor circuit proper having an input addressable by a reference potential, comprising a voltage divider bridging both of the supply terminals and exclusively providing the reference potential, said voltage divider having a first part connected to the first terminal delivering the supply potential for the integrated circuit, said first part being the semiconductor circuit proper to which the reference voltage is applicable, and a second part connected to the second terminal delivering the substrate bias supply potential and generating the reference potential as well as the substrate bias supply potential, said second part having means for delivering to the semiconductor circuit proper said reference potential at a constant value and independently of the respective operating state of the semiconductor circuit proper, the semiconductor circuit proper being directly connected to an output of said second part; further including a source of another reference potential, and wherein said semiconductor circuit proper has an internal terminal for applying a supply potential differing from said reference potential, said internal terminal being directly connected to said first terminal of the semiconductor chip, said second part including a substrate bias generator having a substrate terminal identical with a further supply terminal for carrying said other reference potential, said further supply terminal identical with said substrate terminal being directly connected to said second supply terminal of the semiconductor chip; and wherein said substrate bias generator comprises an amplifier formed of a plurality of cascaded inverters, and including a series circuit between said two supply terminals of the semiconductor chip, said series circuit being formed by said series connection of said substrate bias generator and the semiconductor circuit proper and being bridged by each of the cascaded inverters following the first of said cascaded inverters, said substrate bias generator comprising a field-effect transistor, and the semiconductor circuit proper comprising field-effect transistors, all of said field-effect transistors being of one channel type, said series connection being of said field-effect transistor of said substrate bias generator and current supply paths of the semiconductor circuit proper, each of said following cascaded inverters comprising an MOS driver transistor and a load transistor connected as a diode, said driver transistor having a source terminal connected to said substrate terminal and a drain connected to said one of the two supply terminals of the semiconductor chip simultaneously connected directly to the semiconductor circuit proper, said driver transistors having gates, the gates of the driver transistors of the following cascaded inverters being connected to the respective drain of the driver transistor of the respective preceding cascaded inverter being connected to the drain of the driver transistor of the first cascaded inverter being connected to the drive of the driver transistor of the last cascaded inverter, said driver transistors and said load transistors being of the same channel type as that of the field-effect transistors of the semiconductor circuit proper; and wherein the semiconductor circuit proper controls, via a control output, a circuit part formed in accordance with TTL technology, the semiconductor circuit proper having a signal output connected for controlling an MOS inverter connected between said substrate terminal and said first one of the two supply terminals of the semiconductor chip connected to the semiconductor circuit proper, said MOS inverter having an output forming said TTL control output, said MOS inverter also having a driver transistor matched to the TTL conditions.

Claim 9

Monolithically integrated semiconductor circuit having elements formed on the front side of a monocrystalline semiconductor chip, the semiconductor chip having a first and a second electric terminal addressable by a respective supply potential, the first terminal carrying the supply potential for the integrated circuit, and a second terminal carrying a substrate bias supply potential applied to a substrate region bordering on the rear side of the semiconductor chip, both of the supply potentials being delivered by a d-c power source, the semiconductor circuit proper having an input addressable by a reference potential, comprising a voltage divider bridging both of the supply terminals and exclusively providing the reference potential, said voltage divider having a first part connected to the first terminal delivering the supply potential for the integrated circuit, said first part being the semiconductor circuit proper to which the reference voltage is applicable, and a second part connected to the second terminal delivering the substrate bias supply potential and generating the reference potential as well as the substrate bias supply potential, said second part having means for delivering to the semiconductor circuit proper said reference potential at a constant value and independently of the respective operating state of the semiconductor circuit proper, the semiconductor circuit proper being directly connected to an output of said second part; further including a source of another reference potential, and wherein said semiconductor circuit proper has an internal terminal for applying a supply potential differing from said reference potential, said internal terminal being directly connected to said first terminal of the semiconductor chip, said second part including a substrate bias generator having a substrate terminal identical with a further supply terminal for carrying said other reference potential, said further supply terminal identical with said substrate terminal being directly connected to said second supply terminal of the semiconductor chip; and wherein said substrate bias generator comprises an amplifier formed of a plurality of cascaded inverters, and including a series circuit between said two supply terminals of the semiconductor chip, said series circuit being formed by said series connection of said substrate bias generator and the semiconductor circuit proper and being bridged by each of the cascaded inverters following the first of said cascaded inverters, said substrate bias generator comprising a field-effect transistor, and the semiconductor circuit proper comprising field-effect transistors, all of said field-effect transistors being of one channel type, said series connection being of said field-effect transistor of said substrate bias generator and current supply paths of the semiconductor circuit proper, each of said following cascaded inverters comprising an MOS driver transistor and a load transistor connected as a diode, said driver transistor having a source terminal connected to said substrate terminal and a drain connected to said one of the two supply terminals of the semiconductor chip simultaneously connected directly to the semiconductor circuit proper, said driver transistors having gates, the gates of the driver transistors of the following cascaded inverters being connected to the respective drain of the driver transistor of the respective preceding cascaded inverter being connected to the drain of the driver transistor of the first cascaded inverter being connected to the drive of the driver transistor of the last cascaded inverter, said driver transistors and said load transistors being of the same channel type as that of the field-effect transistors of the semiconductor circuit proper; and wherein the semiconductor circuit proper controls, via a control output, a circuit part formed in accordance with TTL technology, the semiconductor circuit proper having a signal output connected for controlling an MOS inverter connected between said substrate terminal and said first one of the two supply terminals of the semiconductor chip connected to the semiconductor circuit proper, said MOS inverter having an output forming said TTL control output, said MOS inverter also having a driver transistor matched to the TTL conditions.