US4542580A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating n-type silicon regions and associated contacts
Assignee: Computervision Corp
•
Filing: 1983-02-14
•
Granted: 1985-09-24
•
Expires: 2003-02-14
Abstract
Abstract Disclosed are improved bipolar and field effect transistors having n-type silicon regions and associated electrical contacts comprising monocrystalline silicon doped with arsenic and phosphorus. The transistors are fabricated by depositing on a silicon substrate a coating of amorphous silicon comprising a first layer heavily doped with phosphorus and a second layer below the first doped with arsenic. Energy is selectively applied to melt the coating. As the coating resolidifies and cools, arsenic diffuses into the substrate to form shallow n-type regions which are annealed by heat from the coating. Heavily phosphorus-doped, conductive monocrystalline silicon forms above the n-type regions on the substrate, whereas polycrystalline silicon forms above dielectric or other materials. Selective removal of the polysilicon yields shallow, annealed n-type regions integral with self-registered contacts. The resulting transistors have low RC time constants and low contact resistance.
Inventors
- 👤 Peter Delivorias
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:42
CPC Classifications
H; H10; H10P; H10P32/00; H10P32/10; H10P32/17; H10P32/171; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/133; H10D62/137; H10D62/149; H10D62/151; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10P14/00; H10P14/20; H10P14/38; H10P14/3802; H10P14/3806; H10P14/3808; H10P32/14; H10P32/1408; H10P32/1414
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
126 words
A method of fabricating an n-type silicon region and an associated electrical contact at an exposed surface of a p-type monocrystalline silicon substrate bounded by a dielectric, said method comprising the steps of: depositing on said surface an amorphous silicon coating, said coating comprising a first heavily phosphorous-doped layer and an arsenic-doped layer disposed between said phosphorus-doped layer and said surface; selectively applying to said coating a sufficient amount of thermal energy to melt said coating; and allowing a portion of said coating adjacent said surface to crystallize to produce a phosphorus-doped conductive monocrystalline silicon region and to provide heat sufficient to diffuse arsenic into said monocrystalline silicon substrate to form an annealed n-type monocrystalline silicon region in electrical contact with said p-type conductive silicon region.
Claim 2
Independent Claim
126 words
A method of fabricating an n-type silicon region and an associated electrical contact at an exposed surface of a p-type monocrystalline silicon substrate bounded by a dielectric, said method comprising the steps of: depositing on said surface an amorphous silicon coating, said coating comprising a first heavily phosphorous-doped layer and an arsenic-doped layer disposed between said phosphorus-doped layer and said surface; selectively applying to said coating a sufficient amount of thermal energy to melt said coating; and allowing a portion of said coating adjacent said surface to crystallize to produce a phosphorus-doped conductive monocrystalline silicon region and to provide heat sufficient to diffuse arsenic into said monocrystalline silicon substrate to form an annealed n-type monocrystalline silicon region in electrical contact with said p-type conductive silicon region.
Claim 3
Dependent Claim
46 words
The method of claim 1 wherein the amorphous coating is deposited on said dielectric, said method comprising the additional steps of allowing portions of said coating on said dielectric to crystallize as polysilicon and removing the polysilicon portions of said coating without removing monocrystalline silicon regions.
Claim 4
Dependent Claim
26 words
The method of claim 2 wherein said selectively applying step is effected by exposing said coating to a high energy electron beam or a laser beam.
Claim 5
Dependent Claim
18 words
The method of claim 2 wherein said n-type silicon region comprises the emitter of an integrated bipolar transistor.
Claim 6
Dependent Claim
24 words
The method of claim 2 wherein said n-type silicon region comprises the source or drain of an integrated metal oxide semiconductor field effect transistor.
Claim 7
Dependent Claim
26 words
The method of claim 1 wherein said selectively applying step is effected by exposing said coating to a high energy electron beam or a laser beam.
Claim 8
Dependent Claim
18 words
The method of claim 1 wherein said n-type silicon region comprises the emitter of an integrated bipolar transistor.
Claim 9
Dependent Claim
24 words
The method of claim 1 wherein said n-type silicon region comprises the source or drain of an integrated metal oxide semiconductor field effect transistor.
References Cited (Backward Citations)
US3620814A
Cited
US4042006A
Cited
US4041518A
Cited
US3915765A
Cited
US3965385A
Cited
US3957474A
Cited
US3912557A
Cited
US4249141A
Cited
US4214918A
Cited
US4249968A
Cited
US4292091A
Cited
US4260649A
Cited
JPS5615035A
Cited
US4322253A
Cited
US4318752A
Cited
US4340617A
Cited
US4400715A
Cited
US4319954A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-23 | 1989-03-25 | 1989-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-23 | 1993-03-25 | 1993-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-23 | 1997-03-25 | 1997-09-24 | $7700.00 | Window Closed / Lapsed |