Patent US4539742A successfully refreshed from Google Patents.
US4539742A
Expired / Lapsed
US
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Semiconductor device and method for manufacturing the same
Assignee: Toshiba Corp
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Filing: 1982-06-18
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Granted: 1985-09-10
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Expires: 2002-06-18
Abstract
Abstract A semiconductor device wherein collector connecting wiring made of for example n + -type polycrystalline silicon layer is formed by an anisotropic etching which simultaneously engrave a groove in a semiconductor substrate. A collector layer is formed on a non-etched projection, while base contact hole is formed in the lower portion of the groove. Therefore, the base contact hole is not contacted with collector layer, thus preventing the flow of a leakage current and short-circuiting therebetween.
Inventors
- 👤 Koichi Kanzaki
- 👤 Minoru Taguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:09
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D62/117; H10D64/00; H10D64/20; H10D64/23; H10D64/231; H10P; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10P50/644; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
178 words
A method for manufacturing a semiconductor device, comprising the steps of: (a) forming a first impurity region of a second conductivity type in a semiconductor layer of a first conductivity type which is formed above a semiconductor substrate; (b) selectively forming a conductive film of said first conductivity type on a portion of said first impurity region, said film being covered by a first insulating layer; (c) forming a groove by anistropically etching portions of said first impurity region using said first insulating layer as a mask, thereby defining a projecting region supporting said conductive film and said first insulating layer and having side surfaces extending below said conductive film; (d) forming a second insulating layer covering the grooved surface formed in step (c); (e) forming a second impurity region of said second conductivity type at the bottom of said groove; (f) selectively etching said second insulating layer to leave said second insulating layer on the side surfaces of said groove defining said projecting region; and (g) depositing a wiring layer electrically connected to said second impurity region.
Claim 2
Independent Claim
178 words
A method for manufacturing a semiconductor device, comprising the steps of: (a) forming a first impurity region of a second conductivity type in a semiconductor layer of a first conductivity type which is formed above a semiconductor substrate; (b) selectively forming a conductive film of said first conductivity type on a portion of said first impurity region, said film being covered by a first insulating layer; (c) forming a groove by anistropically etching portions of said first impurity region using said first insulating layer as a mask, thereby defining a projecting region supporting said conductive film and said first insulating layer and having side surfaces extending below said conductive film; (d) forming a second insulating layer covering the grooved surface formed in step (c); (e) forming a second impurity region of said second conductivity type at the bottom of said groove; (f) selectively etching said second insulating layer to leave said second insulating layer on the side surfaces of said groove defining said projecting region; and (g) depositing a wiring layer electrically connected to said second impurity region.
Claim 3
Dependent Claim
16 words
The method according to claim 1 wherein said conductive film has a Schottky junction formed thereon.
Claim 4
Dependent Claim
30 words
The method according to claim 1 wherein an impurity of said second conductivity type is ion-implanted through said second insulating layer to form said second impurity region in step (e).
Claim 5
Dependent Claim
77 words
The method according to claim 1 wherein said conductive film formed in step (b) comprises a polycrystalline silicon layer doped with an impurity of said first conductivity type, and wherein said method further comprises the step of forming a doped region of said first conductivity type in said first impurity region formed in step (a) using said polycrystalline silicon layer as a diffusion source, at the same time said second impurity region is formed in step (e).
Claim 6
Dependent Claim
33 words
The method according to claim 4 wherein the bottom surface of said groove is below the lower surface of said doped region formed by diffusin of an impurity from said polycrystalline silicon layer.
Claim 7
Dependent Claim
18 words
The method according to claim 5 wherein the depth of said groove is approximately 0.15 to 0.7 μm.
Claim 8
Dependent Claim
26 words
The method according to claim 1 wherein said first conductivity type is an n conductivity type, and said second conductivity type is a p conductivity type.
Claim 9
Dependent Claim
76 words
The method according to claim 1 wherein said semiconductor layer of said first conductivity type constitutes an emitter section of an npn transistor of an I 2 L gate, said semiconductor layer of said second conductivity type constitutes a base section of said npn transistor and an emitter section of a pnp transistor of said I 2 L gate, and said conductive film of said first conductivity type constitutes a collector section of said npn transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-09 | 1989-03-11 | 1989-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-09 | 1993-03-11 | 1993-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-09 | 1997-03-11 | 1997-09-10 | $7700.00 | Window Closed / Lapsed |