EP0030147A1
Expired / Lapsed
EP
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Method for manufacturing a semiconductor integrated circuit
Assignee: Toshiba Corp
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Filing: 1980-11-28
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Granted: —
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Expires: 2000-11-28
Abstract
Abstract A method for manufacturing a semiconductor integrated circuit includes diffusing an impurity of a second conductivity type into polycrystalline silicon layers (10) formed on a first conductivity region (5) in a substrate (1) to form second conductivity regions (13), the polycrystalline silicon layers (10) constituting first electrode wirings to the second conductivity regions (13); forming a thick oxidation film (11) on the polycrystalline silicon layers (10) and a thin oxidation film (12) on the exposed surface of the substrate by a heat oxidation treatment; and removing the thin oxidation film (12) to form a second electrode wiring to the first conductivity region (5), said second electrode wiring being insulated from the polycrystalline silicon layers (10) by the thick oxidation film (11). The method provides integrated circuits such as 1 2 L circuits which are capable of high speed operation and a high packaging density.
Inventors
- 👤 Koichi Kanzaki
- 👤 Minoru Taguchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 19:00
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/0116; H10D84/02; H10D84/03; H10D84/038; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; H10P76/00; H10P76/40; H10P95/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
179 words
A method for manufacturing a semiconductor integrated circuit characterized by comprising the steps of: selectively forming a polycrystalline silicon layer containing an impurity of second conductivity type on a first conductivity type region formed in a semiconductor substrate; forming both a thick oxidation film on said polycrystalline silicon layer and a thin oxidation film on the exposed surface of said substrate by a heat oxidation treatment; diffusing said impurity of second conductivity type from said polycrystalline silicon layer into said first conductivity type region in said substrate to form second conductivity type regions, said polycrystalline silicon layer constituting a first electrode wiring layer connected with said second conductivity type regions; removing said thin oxidation film by etching said oxidation films to leave said thick oxidation film on said polycrystalline silicon layers for forming a contact hole to said first conductivity type region; and forming a second electrode wiring layer insulated from said first electrode wiring layer of the polycrys- stalline silicon by said oxidation film formed thereon and connected with said first conductivity type region through said contact hole.
Claim 2
Independent Claim
179 words
A method for manufacturing a semiconductor integrated circuit characterized by comprising the steps of: selectively forming a polycrystalline silicon layer containing an impurity of second conductivity type on a first conductivity type region formed in a semiconductor substrate; forming both a thick oxidation film on said polycrystalline silicon layer and a thin oxidation film on the exposed surface of said substrate by a heat oxidation treatment; diffusing said impurity of second conductivity type from said polycrystalline silicon layer into said first conductivity type region in said substrate to form second conductivity type regions, said polycrystalline silicon layer constituting a first electrode wiring layer connected with said second conductivity type regions; removing said thin oxidation film by etching said oxidation films to leave said thick oxidation film on said polycrystalline silicon layers for forming a contact hole to said first conductivity type region; and forming a second electrode wiring layer insulated from said first electrode wiring layer of the polycrys- stalline silicon by said oxidation film formed thereon and connected with said first conductivity type region through said contact hole.
Claim 3
Dependent Claim
58 words
A method according to claim 1, further comprising the step of diffusing by ion implantation and slamping an impurity of first conductivity type through said thin oxidation film formed by a heat oxidation treatment on the exposed surface of said substrate into said first conductivity type region to form a high impurity concentration region of first conductivity type.
Claim 4
Dependent Claim
37 words
A method according to claim 1, wherein said second electorde wiring layer is formed by forming a lower layer of polycrystalline silicon containing an impurity of first conductivity type and an upper layer of a metal thereon.
Claim 5
Dependent Claim
47 words
A method according to claim 1, further comprising the step of covering, before etching said oxidation films, said thin oxidation film at the peripheries of said first conductivity type region with a photoresist to form eaves protruding inwardly from the peripheries of said region during the etching.
Claim 6
Dependent Claim
64 words
A method according to claim 1, further comprising the step of covering, before etching said oxidation films, said thin oxidation film at the peripheries of said first conductivity type region with aluminum oxide or silicon nitrate, for forming eaves of said thin oxidation film protruding inwardly from the peripheries of said region during etching, with said aluminum oxide or silicon nitrate layer being left.
Claim 7
Dependent Claim
31 words
A method according to claim 1, 2, 3, 4, or 5, wherein the concentration of said impurity of second conductivity type contained in said polycrystalline silicon is over 10 /cm .
Claim 8
Dependent Claim
46 words
A method according to claim 1, 2, 3, 4, or 5, wherein the heat oxidation treatment for forming said oxidation films on said polycrystalline silicon layer and the exposed surface of said substrate is performed in an oxygen atmosphere at a temperature of 700 to 900°C.
Claim 9
Dependent Claim
65 words
A method according to claim 1, wherein said first conductivity type region constitutes the base of an npn transistor and the emitter of a pnp transistor of an 1 2 L gate, and the impurity of second conductivity type is diffused from said polycrystalline silicon layers to said first conductivity type region to form said second conductivity type regions as collectors of said npn transistor.
References Cited (Backward Citations)
US3928095A
Cited
US4210993A
Cited
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