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US4476522A
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Programmable peripheral processing controller with mode-selectable address register sequencing
Assignee: International Business Machines Corp
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Filing: 1981-03-09
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Granted: 1984-10-09
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Expires: 2001-03-09
Abstract
Abstract A peripheral processing controller controls time-shared access to a memory by specialized peripheral devices. The specialized peripheral devices process data independently of a central processor that simply supervises the system. The peripheral processing controller uses predetermined modes of memory space allocation for the various peripheral devices. A memory address register in the controller is assigned to each peripheral device. In addition, each MAR has one or more predefined modes of memory space allocation and, when active, controls memory access for its assigned peripheral device. The modes also define the size of the block of space allocated and whether memory access scrolls through various blocks of space or jumps between blocks of space. The controller also detects when a peripheral device has consumed all the space in a block. Further, for those MAR's having more than one mode of space allocation, the controller selects the mode appropriate for the peripheral device requesting access to the memory.
Inventors
- 👤 Kenneth A. Bushaw
- 👤 Darwin P. Rackley
- 👤 Milton H. Woodward
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 12:39
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F13/14; G06F13/16; G06F13/18; G06F12/00; G06F12/02; G06F12/0223; G06F12/0284
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
176 words
A peripheral processing controller in a system having a plurality of peripheral devices processing data directly with a memory and independently of a central processor, said controller providing access from each peripheral device to the memory and comprising: a plurality of memory address registers, each register associated with one of the peripheral devices and assigned an access mode, defining a memory space addressing sequence, and a memory space allocation; said memory address registers being initialized to a starting address; means for accessing the memory with the starting address from a selected one of said memory address registers, said accessing means responsive to said access mode for advancing the access address through memory space in the address sequence controlled by said access mode as the peripheral device associated with the selected register processes data with the memory; detection means responsive to the memory space allocation assigned to the selected memory address register for detecting when a block of memory space allocated to the peripheral device associated with the selected register has been consumed by the peripheral device.
Claim 2
Dependent Claim
176 words
A peripheral processing controller in a system having a plurality of peripheral devices processing data directly with a memory and independently of a central processor, said controller providing access from each peripheral device to the memory and comprising: a plurality of memory address registers, each register associated with one of the peripheral devices and assigned an access mode, defining a memory space addressing sequence, and a memory space allocation; said memory address registers being initialized to a starting address; means for accessing the memory with the starting address from a selected one of said memory address registers, said accessing means responsive to said access mode for advancing the access address through memory space in the address sequence controlled by said access mode as the peripheral device associated with the selected register processes data with the memory; detection means responsive to the memory space allocation assigned to the selected memory address register for detecting when a block of memory space allocated to the peripheral device associated with the selected register has been consumed by the peripheral device.
Claim 3
Dependent Claim
40 words
The apparatus of claim 1 and in addition: at least one of said registers having more than one assigned access mode; means initialized by the central processor for selecting the access mode assigned to registers having more than one mode.
Claim 4
Dependent Claim
71 words
The apparatus of claim 2 and in addition: said accessing means is responsive to the selected access mode to jump the memory address to the beginning of the next successive block in a succession of blocks of memory space, after the currently accessed block of space is consumed, and to return the memory address to the first block in the succession of blocks of space after all blocks have been accessed.
Claim 5
Dependent Claim
28 words
The apparatus of claim 2 and in addition: said accessing means is responsive to the selected access mode to scroll memory addressing through multiple blocks of memory space.
Claim 6
Dependent Claim
37 words
The apparatus of claim 2 and in addition: said accessing means is responsive to the selected access mode to sequence the memory address alternately between two blocks of memory space after each block of space is consumed.
Claim 7
Dependent Claim
71 words
The apparatus of claim 2 wherein said selecting means comprises: mode storage means for storing an access mode, said mode storage means being initialized by the central processor to a selected access mode; means responsive to the selection of a memory address register for enabling said mode storage means to pass the selected access mode to said accessing means when the memory address register assigned the selected access mode is selected.
Claim 8
Dependent Claim
37 words
The apparatus of claim 6 and in addition: said accessing means is responsive to the selected access mode to sequence the memory address alternately between two blocks of memory space after each block of space is consumed.
Claim 9
Dependent Claim
71 words
The apparatus of claim 6 and in addition: said accessing means is responsive to the selected access mode to jump the memory address to the beginning of the next successive block in a succession of blocks of memory space after the currently accessed block of space is consumed, and to return the memory address to the first block in the succession of blocks of space after all blocks have been accessed.
Claim 10
Dependent Claim
28 words
The apparatus of claim 6 and in addition: said accessing means is responsive to the selected access mode to scroll memory addressing through multiple blocks of memory space.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-09 | 1988-04-09 | 1988-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-09 | 1992-04-09 | 1992-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-09 | 1996-04-09 | 1996-10-09 | $7700.00 | Window Closed / Lapsed |