Process for making CMOS field-effect transistors with self-aligned guard rings utilizing special masking and ion implantation

Claim 1

A process for making complementary MOS field-effect transistors with contiguous channel stops in a silicon substrate of one conductivity type overlain by an oxide layer, comprising the steps of: (a) forming a first and a second patch of shielding material on said oxide layer above spaced-apart first and second regions of said substrate; (b) injecting first impurities of said one conductivity type through said oxide layer into zones of said substrate immediately adjoining said first and second regions, including an intermediate section separating said first and second regions, thereby enhancing the conductivity of said zones over that of said substrate; (c) covering said first patch and at least one immediately adjoining first zone of said oxide layer, including a portion thereof overlying part of said intermediate section, with a masking layer while leaving uncovered said second patch and at least one immediately adjoining second zone of said oxide layer, including a portion thereof overlying another part of said intermediate section; (d) injecting second impurities of the opposite conductivity type through said second patch and through said second zone in a quantity sufficient to produce a well of said opposite conductivity type in said second region but insufficient to invert the conductivity in a substrate portion underlying said second zone enhanced by the first impurities injected in step (b); (e) subjecting said substrate to a first heat treatment in a nonoxidizing atmosphere at a high temperature and for a time sufficient to let the first impurities injected in step (b) diffuse to a predetermined extent into said first and second regions while letting the second impurities of said second region diffuse deeper into the substrate; (f) injecting more of said second impurities into said underlying substrate portion in a quantity sufficient to impart thereto a conductivity of inverted type enhanced over that of said second region while preserving the enhanced nonverted conductivity of a substrate portion in the vicinity of said first region to leave a channel stop of said one conductivity type next to a pedestal of substrate conductivity beneath said first patch; (g) subjecting said substrate to a second heat treatment at a temperature lower than that of said first heat treatment in step (e) and for a time enabling the impurities injected in step (f) to diffuse to an extent expanding the area of enhanced conductivity to the boundary of the well produced in step (d), thereby forming a second channel stop of said opposite conductivity type next to said well beneath said second patch; (h) thermally expanding said oxide layer, following removal of said masking layer, predominantly in areas free from said patches; (i) removing said patches together with underlying portions of said oxide layer, thereby opposing said first and second regions except for a residue of said oxide layer extending across each of said regions and dividing same into source and drain areas while forming an insulating gate support; and (j) introducing impurities of said one conductivity type and of said opposite conductivity type into the source and drain areas of said second and said first region, respectively.