Patent US4461072A successfully refreshed from Google Patents.
US4461072A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for preparing an insulated gate field effect transistor
Assignee: Fujitsu Ltd
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Filing: 1983-05-20
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Granted: 1984-07-24
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Expires: 2003-05-20
Abstract
Abstract Disclosed here is an IGFET formed on the single crystal silicon substrate where the major plane surface is deviated within the range from 22 degree to 34 degree toward the crystallographic surface {1,1,1} from {1,0,0} or on the silicon epitaxial layer formed on said substrate. Here, generation of silicon nitride is suppressed, which is newly formed under the mask in the selective oxidation process using the silicon nitride as the mask and also is the main cause of lowering the breakdown voltage of the gate insulating film. In addition, various kinds of functional characteristics depending on the crystallographic surface orientation are not interfered at all. Thereby, the present invention can offer an IGFET which drastically improved the breakdown voltage failure rate of the gate insulating film while keeping the functional characteristics at the best condition.
Inventors
- 👤 Kunihiko Wada
- 👤 Motoo Nakano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:44
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D62/00; H10D62/40; H10D62/405; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13; Y; Y10; Y10S; Y10S438/00; Y10S438/973
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
212 words
A method of manufacturing an insulated gate field effect transistor comprising the steps of forming a silicon dioxide film on a single crystal silicon substrate having a surface deviated by an angle within a range of from 30.3° to 34° from the {100} crystallographic surface toward the {111} crystallographic surface, forming a silicon nitride film on said silicon dioxide film, patterning said silicon nitride film to include a portion remaining on a forming area for said insulated gate field effect transistor on said substrate wherein said forming area includes areas corresponding to the source and drain regions of said insulated gate field effect transistor, forming a thermally oxidized film selectively on and embedded in said substrate using the remaining silicon nitride film as a mask, removing said remaining silicon nitride film from said silicon dioxide film, removing said silicon dioxide film on said forming area of said substrate, forming a gate insulating film on said surface of said substrate in said forming area, said thermally oxidized film having a greater thickness than said gate insulating film, forming a gate electrode on said gate insulating film for providing an electric field to said substrate across said gate insulating film; and forming said source and drain regions using said gate electrode as a mask.
Claim 2
Independent Claim
212 words
A method of manufacturing an insulated gate field effect transistor comprising the steps of forming a silicon dioxide film on a single crystal silicon substrate having a surface deviated by an angle within a range of from 30.3° to 34° from the {100} crystallographic surface toward the {111} crystallographic surface, forming a silicon nitride film on said silicon dioxide film, patterning said silicon nitride film to include a portion remaining on a forming area for said insulated gate field effect transistor on said substrate wherein said forming area includes areas corresponding to the source and drain regions of said insulated gate field effect transistor, forming a thermally oxidized film selectively on and embedded in said substrate using the remaining silicon nitride film as a mask, removing said remaining silicon nitride film from said silicon dioxide film, removing said silicon dioxide film on said forming area of said substrate, forming a gate insulating film on said surface of said substrate in said forming area, said thermally oxidized film having a greater thickness than said gate insulating film, forming a gate electrode on said gate insulating film for providing an electric field to said substrate across said gate insulating film; and forming said source and drain regions using said gate electrode as a mask.
Claim 3
Dependent Claim
28 words
The method of claim 1, wherein the substrate comprises a single crystal silicon base plate and a silicon epitaxial layer formed on the single crystal silicon base plate.
Claim 4
Dependent Claim
12 words
The method of claim 1, wherein said gate electrode is polycrystalline silicon.
Claim 5
Dependent Claim
39 words
The method of claim 1, comprising selecting said single crystal silicon substrate have a first conductivity type, and forming source and drain regions in said substrate on each side of said gate insulating film with the opposite conductivity type.
Claim 6
Dependent Claim
13 words
The method of claim 1, wherein said gate insulating film is silicon dioxide.
Claim 7
Dependent Claim
50 words
The method of claim 5, comprising selecting said single crystal silicon substrate to have a first conductivity type, implanting ions of the opposite conductivity type into said single-crystal substrate adjacent said gate insulating film, and forming source and drain regions having said opposite conductivity type by activating the implanted ions.
Claim 8
Dependent Claim
19 words
The method of claim 1, wherein said silicon epitaxial layer has a thickness of not less than 3 microns.
Claim 9
Dependent Claim
47 words
The method of claim 1, comprising selecting said single crystal silicon substrate to have a first conductivity type and, injecting impurities of said first conductivity type into said surface of said substrate using said remaining silicon nitride film as a mask to form a channel stop region.
Claim 10
Dependent Claim
51 words
The method of claim 1, comprising selecting said single crystal silicon substrate to have a first conductivity type, implanting ions of the opposite conductivity type into said single-crystal substrate adjacent said gate insulating film, and forming said source and drain regions having said opposite conductivity type by activating the implanted ions.
Claim 11
Independent Claim
290 words
A method of manufacturing an insulated gate field effect transistor comprising the steps of forming a silicon dioxide film on a single crystal silicon substrate of a first conductivity type and having a surface deviated by an angle within the range from above 30.3° to substantially 34° with respect to the {100} crystallographic surface towards the {111} crystallographic surface, forming a silicon nitride film on said silicon dioxide film, patterning said silicon nitride film to remain on a forming area for said insulated gate field effect transitor on said substrate by photoetching, injecting ions of said first conductivity type into said surface of said substrate using the remaining silicon nitride film as a mask to form a channel stop region, forming a thick silicon dioxide film by thermal oxidation using said remaining silicon nitride film as a mask, removing said remaining silicon nitride film on said silicon dioxide film, removing said silicon dioxide film on said forming region of said substrate, forming a gate insulating film on said single crystal silicon substrate in said forming region, forming a polycrystalline silicon film on said gate insulating film, patterning said polycrystalline silicon film to remain as a gate electrode on said gate insulating film by photoetching, selectively implanting ions of the opposite conductivity type into said single crystal silicon substrate using said gate electrode as a mask, forming source and drain regions having said opposite conductivity type by activating the implanted ions, forming a phosphorus silicate glass film on the upper surface of said substrate, providing windows for contacting said source and drain regions by photoetching said phosphorus silicate glass film and said gate insulating film, and providing electrodes on said phosphorus silicate glass film for contacting said source and drain regions.
Claim 12
Independent Claim
290 words
A method of manufacturing an insulated gate field effect transistor comprising the steps of forming a silicon dioxide film on a single crystal silicon substrate of a first conductivity type and having a surface deviated by an angle within the range from above 30.3° to substantially 34° with respect to the {100} crystallographic surface towards the {111} crystallographic surface, forming a silicon nitride film on said silicon dioxide film, patterning said silicon nitride film to remain on a forming area for said insulated gate field effect transitor on said substrate by photoetching, injecting ions of said first conductivity type into said surface of said substrate using the remaining silicon nitride film as a mask to form a channel stop region, forming a thick silicon dioxide film by thermal oxidation using said remaining silicon nitride film as a mask, removing said remaining silicon nitride film on said silicon dioxide film, removing said silicon dioxide film on said forming region of said substrate, forming a gate insulating film on said single crystal silicon substrate in said forming region, forming a polycrystalline silicon film on said gate insulating film, patterning said polycrystalline silicon film to remain as a gate electrode on said gate insulating film by photoetching, selectively implanting ions of the opposite conductivity type into said single crystal silicon substrate using said gate electrode as a mask, forming source and drain regions having said opposite conductivity type by activating the implanted ions, forming a phosphorus silicate glass film on the upper surface of said substrate, providing windows for contacting said source and drain regions by photoetching said phosphorus silicate glass film and said gate insulating film, and providing electrodes on said phosphorus silicate glass film for contacting said source and drain regions.
Claim 13
Independent Claim
312 words
A method of manufacturing an insulated gate field effect transistor comprising the steps of forming a silicon epitaxial layer with a first conductivity type on a single crystal silicon substrate having a surface deviated by an angle within the range from above 30.3° to substantially 34°, with respect to the {100} crystallographic surface towards the {111} crystallographic surface, forming a silicon dioxide film on said silicon epitaxial layer, forming a silicon nitride film on said silicon dioxide film, patterning said silicon nitride film to remain on a forming area of said epitaxial layer for said insulated gate field effect transistor by photoetching, injecting ions of said first conductivity type into the surface of said silicon epitaxial layer using the remaining silicon nitride film as a mask to form a channel stop region, forming a thick silicon dioxide film by thermal oxidation on and embedded in said epitaxial layer using the remaining silicon nitride film as a mask for thermal oxidation, removing the remaining silicon nitride film from said silicon dioxide film, removing said silicon dioxide film on said forming area, forming a gate insulating film on said silicon epitaxial layer in said forming area, forming a polycrystalline silicon film on said gate insulating film, patterning said polycrystalline silicon film to provide a gate electrode on said gate insulating film by photoetching, implanting ions of the opposite conductivity type into an area of said silicon epitaxial layer through said gate insulating film using said gate electrode as a mask, forming source and drain regions having said opposite conductivity type in said silicon epitaxial layer by activating the implanted ions, forming a phosphorus silicate glass film on the upper surface of said substrate, providing windows for contacting said source and drain regions by photoetching said gate insulating film, and providing electrodes on said phosphorus silicate glass film for contacting said source and drain regions.
Claim 14
Independent Claim
312 words
A method of manufacturing an insulated gate field effect transistor comprising the steps of forming a silicon epitaxial layer with a first conductivity type on a single crystal silicon substrate having a surface deviated by an angle within the range from above 30.3° to substantially 34°, with respect to the {100} crystallographic surface towards the {111} crystallographic surface, forming a silicon dioxide film on said silicon epitaxial layer, forming a silicon nitride film on said silicon dioxide film, patterning said silicon nitride film to remain on a forming area of said epitaxial layer for said insulated gate field effect transistor by photoetching, injecting ions of said first conductivity type into the surface of said silicon epitaxial layer using the remaining silicon nitride film as a mask to form a channel stop region, forming a thick silicon dioxide film by thermal oxidation on and embedded in said epitaxial layer using the remaining silicon nitride film as a mask for thermal oxidation, removing the remaining silicon nitride film from said silicon dioxide film, removing said silicon dioxide film on said forming area, forming a gate insulating film on said silicon epitaxial layer in said forming area, forming a polycrystalline silicon film on said gate insulating film, patterning said polycrystalline silicon film to provide a gate electrode on said gate insulating film by photoetching, implanting ions of the opposite conductivity type into an area of said silicon epitaxial layer through said gate insulating film using said gate electrode as a mask, forming source and drain regions having said opposite conductivity type in said silicon epitaxial layer by activating the implanted ions, forming a phosphorus silicate glass film on the upper surface of said substrate, providing windows for contacting said source and drain regions by photoetching said gate insulating film, and providing electrodes on said phosphorus silicate glass film for contacting said source and drain regions.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1987-07-24 | 1988-01-23 | 1988-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-24 | 1992-01-23 | 1992-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-24 | 1996-01-23 | 1996-07-24 | $7700.00 | Window Closed / Lapsed |