Adjacent bilinear photosite imager

Claim 2

A high density charge coupled device imaging array (28) on a single integrated circuit chip, wherein the improvement is characterized by, a first row (32) of photosite means deposited on said integrated circuit chip, said photosite means being sensitive to applied light information representative of one scan line of data, a second row (30) of photosite means deposited on said integrated circuit chip adjacent to and contiguous with said first row of photosite means, said second row of photosite means being offset from said first row of photosite means approximately one-half the length of individual photosite means on said first row such that said second row of photosite means are sensitive to applied light information in the same said one scan line of data intermediate the photosite means in said first row of photosite means, said first and second rows of photosite means comprising a bilinear array of photosite means.

Claim 3

The imaging array as set forth in claim 1 further including, a storage register (38) deposited on said integrated circuit chip adjacent to said first row (32) of photosite means to receive and store the bits of information detected by said first row of photosite means (32) and converted to electronic charge information.

Claim 4

The imaging array as set forth in claim 2 further including, a first shift register means (42) deposited on said integrated circuit chip adjacent to said second row (30) of photosite means to receive and store the bits of light information detected by said second row of photosite means and converted to electronic charge information, and a second shift register means (44) deposited on said integrated circuit chip adjacent to said storage register means (38) to receive and store said bits of light information received by said storage register means (38) from said first row (32) of photosite means, said second shift register means and said first shift register means (42) receiving the bits of light information therefor at the same time period.

Claim 5

The imaging array as set forth in claim 3 further including, transfer gate means (34, 36, 40) between the first row (32) of photosite means and the storage register means (38), the storage register means (38) and second shift register means (44), and the second row (30) of photosite means and the first shift register means (42), said transfer gate means also being deposited on said integrated circuit chip to provide paths for the movement of the electronic charge information.

Claim 6

A high density charge coupled device imaging array (28) on a single integrated circuit chip for use in detection of information contained in repetitive line scans, comprising: a first row (32) of photosite means formed on said integrated circuit chip, said photosite means being sensitive to applied light information in one scan line in the form of data bits by depositing electronic charge in the substrate of said chip in response to said applied light information, a second row (32) of photosite means formed on said integrated circuit chip immediately adjacent to and contiguous with said first row (32) of photosite means, said second row (32) of photosite means being offset from said first row of photosite means intermediate the centers of the photosite means in said first row of photosite means such that said second row of photosite means are sensitive to applied light information in one scan line in the form of data bits by depositing electronic charge in the substrate of said chip in response to applied light information intermediate the photosite means on said first row of photosite means, said first and second rows of photosite means comprising a bilinear array of photosite means which consecutively scan the same lines of information in a raster scan type of arrangement.

Claim 7

A high density charge coupled device imaging array (28) on a single integrated circuit chip for use in detection of information contained in repetitive line scans, comprising: a first row (32) of photosite means formed on said integrated circuit chip, said photosite means being sensitive to applied light information in one scan line in the form of data bits by depositing electronic charge in the substrate of said chip in response to said applied light information, a second row (32) of photosite means formed on said integrated circuit chip immediately adjacent to and contiguous with said first row (32) of photosite means, said second row (32) of photosite means being offset from said first row of photosite means intermediate the centers of the photosite means in said first row of photosite means such that said second row of photosite means are sensitive to applied light information in one scan line in the form of data bits by depositing electronic charge in the substrate of said chip in response to applied light information intermediate the photosite means on said first row of photosite means, said first and second rows of photosite means comprising a bilinear array of photosite means which consecutively scan the same lines of information in a raster scan type of arrangement.

Claim 8

The imaging array as set forth in claim 5 further including: a storage register means (38) formed on said integrated circuit chip adjacent to said first row (32) of photosite means to receive and store said data bits from a scan line of information detected by said first row of photosite means (32).

Claim 9

The imaging array as set forth in claim 6 further including: a first shift register means (42) formed on said integrated circuit chip adjacent to said second row (30) of photosite means to receive and store the intermediate data bits from said same scan line of information as detected by said second row of photosite means, and a second shift register means (44) formed on said integrated circuit chip adjacent to said storage register means (38) to receive and store said data bits received by said storage register means (38) from said first row (32) of photosite means, said second shift register means (44) and said first shift register means (42) receiving the data bits and the intermediate data bits therefor at the same time period.

Claim 10

The imaging array as set forth in claim 7 further including: transfer gate means (34, 36, 40) between the first row (32) of photosite means and the storage register means (38), the storage register means (38) and second shift register means (44), and the second row (30) of photosite means and the first shift register means (42), said transfer gate means being formed on said integrated circit chip to provide paths for the movement of the electronic charge information representing said data bits.

Claim 11

A high density charge coupled device imaging array (28) on a single integrated circuit chip, comprising: a first row (32) of photosite means deposited on said integrated circuit chip, said photosite means being sensitive to applied light information, a second row of photosite means deposited on said integrated circuit chip adjacent to and contiguous with said first row of photosite means, said second row of photosite means being offset from said first row of photosite means approximately one-half the length of individual photosite means on said first row such that said second row of photosite means are sensitive to applied light information intermediate the photosite means in said first row of photosite means, said first and second rows of photosite means comprising a bilinear array of photosite means, each of said photosite means in said first and second rows having width, w, and height, h, approximately related by w=2kh, where k is the ratio of the horizontal sampling pitch, S x to vertical sampling pitch, S y .

Claim 12

A high density charge coupled device imaging array (28) on a single integrated circuit chip, comprising: a first row (32) of photosite means deposited on said integrated circuit chip, said photosite means being sensitive to applied light information, a second row of photosite means deposited on said integrated circuit chip adjacent to and contiguous with said first row of photosite means, said second row of photosite means being offset from said first row of photosite means approximately one-half the length of individual photosite means on said first row such that said second row of photosite means are sensitive to applied light information intermediate the photosite means in said first row of photosite means, said first and second rows of photosite means comprising a bilinear array of photosite means, each of said photosite means in said first and second rows having width, w, and height, h, approximately related by w=2kh, where k is the ratio of the horizontal sampling pitch, S x to vertical sampling pitch, S y .

Claim 13

The imaging array as set forth in claim 9 further including, a storage register means (38) deposited on said integrated circuit chip adjacent to said first row (32) of photosite means to receive and store the bits of information detected by said first row of photosite means (32) and converted to electronic charge information.

Claim 14

The imaging array as set forth in claim 10 further including, a first shift register means (42) deposited on said integrated circuit chip adjacent to said second row (30) of photosite means to receive and store the bits of light information detected by said second row of photosite means and converted to electronic charge information, and a second shift register means (44) deposited on said integrated circuit chip adjacent to said storage register means (38) to receive and store said bits of light information received by said storage register means (38) from said first row (32) of photosite means, and said second shift register means and said first shift register means (42) receiving the bits of light information therefor at the same time period.

Claim 15

The imaging array as set forth in claim 11 further including, transfer gate means (34, 36, 40) between the first row (32) of photosite means and the storage register means (38), the storage register means (38) and second shift register means (44), and the second row (30) of photosite means and the first shift register means (42) said transfer gate means also being deposited on said integrated circit chip to provide paths for the movement of the electronic charge information.