US3940602A
Expired / Lapsed
US
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Signal processing imager array using charge transfer concepts
Assignee: United States Department of the Navy
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Filing: 1974-09-23
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Granted: 1976-02-24
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Expires: 1994-09-23
Abstract
Abstract A signal processing sensor which utilizes a combination of charge transfer devices and signal processing concepts which simultaneously measures the incident optical signal and performs a linear transformation upon that signal. Two CCD registers are arranged on either side of a photodiode array. Independent control of the transfer gates which control the flow of information stored in the depletion region of the photodiodes results in independent functioning of the two CCD registers. The difference between the charge in the two registers is taken at the output in order to provide both positive and negative weight for the data pattern that is to be convolved or correlated.
Inventors
- 👤 Isaac Lagnado
- 👤 Harper J. Whitehouse
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 05:07
CPC Classifications
H; H04; H04N; H04N19/00; H04N19/60; H04N25/00; H04N25/60; H04N25/62; H04N25/625; H04N25/70; H04N25/701; H04N25/71; H04N25/713; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/15; H10F39/152
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
122 words
An apparatus for image sensing and mathematical transformation comprising: an array of optical sensors for sensing an image and storing a series of charge signals representative of said image; first and second CCD shift registers, each said CCD shift register comprising a plurality of bits; first and second distinct independently controlled transfer gate means for controlling the transfer of said charge signals from said array of optical sensors to said first and second CCD shift registers; a plurality of diffusion stops arranged to permit the transfer of each charge signal of said series of charge signals from each element of said array of optical sensors to one of said plurality of bits in either of said first and second CCD shift registers.
Claim 2
Independent Claim
122 words
An apparatus for image sensing and mathematical transformation comprising: an array of optical sensors for sensing an image and storing a series of charge signals representative of said image; first and second CCD shift registers, each said CCD shift register comprising a plurality of bits; first and second distinct independently controlled transfer gate means for controlling the transfer of said charge signals from said array of optical sensors to said first and second CCD shift registers; a plurality of diffusion stops arranged to permit the transfer of each charge signal of said series of charge signals from each element of said array of optical sensors to one of said plurality of bits in either of said first and second CCD shift registers.
Claim 3
Dependent Claim
22 words
The apparatus of claim 1 further comprising timing means for outputting a sequence of timing pulses to said array of optical sensors.
Claim 4
Dependent Claim
15 words
The apparatus of claim 1 wherein said array of optical sensors comprises a photodiode array.
Claim 5
Dependent Claim
15 words
The apparatus of claim 1 wherein said array of optical sensors comprises photosensitive MOS capacitors.
Claim 6
Dependent Claim
37 words
The apparatus of claim 1 further comprising summing means coupled to said first and second CCD shift registers for subtracting the output of said second CCD shift register from the output of said first CCD shift register.
Claim 7
Dependent Claim
97 words
. The apparatus of claim 5 further comprising timing means for outputting a sequence of timing pulses representative of a signal sequence to said first and second transfer gate means and for providing a series of clock pulses for shifting said first and second CCD shift registers, the interval between each said timing pulse determining the integration time of said optical sensors; whereby in response to said sequence of timing pulses and clock pulses said summing means provides an output waveform representative of the convolution of said sries of charge signals with said sequence of timing pulses.
Claim 8
Dependent Claim
96 words
The apparatus of claim 5 further comprising timing means for outputting a sequence of timing pulses representative of a signal sequence to said first and second transfer gate means and for providing a series of clock pulses for shifting said first and second CCD shift registers, the interval between each said timing pulse determining the integration time of said optical sensors; whereby in response to said sequence of timing pulses and clock pulses said summing means provides an output waveform representative of the correlation of said series of charg signals with said sequence of timing pulses.
Claim 9
Independent Claim
132 words
A method of computing the convolution of first and second discrete functions comprising the steps of: storing a series of charge signals representative of said first function in an array of photosensors; transferring a first set of said charge signals to a first CCD shift register and a second set of said charge signals to a second CCD shift register in accordance with a predetermined sequence of timing pulses representative of said second function; shifting said first and second CCD shift registers in accordance with a predetermined series of clock pulses; subtracting in an adder the output of said second CCD shift register from the output of said first CCD shift register subsequent to each shifting operation; whereby the output of said adder is the convolution of said first and second functions.
Claim 10
Independent Claim
132 words
A method of computing the convolution of first and second discrete functions comprising the steps of: storing a series of charge signals representative of said first function in an array of photosensors; transferring a first set of said charge signals to a first CCD shift register and a second set of said charge signals to a second CCD shift register in accordance with a predetermined sequence of timing pulses representative of said second function; shifting said first and second CCD shift registers in accordance with a predetermined series of clock pulses; subtracting in an adder the output of said second CCD shift register from the output of said first CCD shift register subsequent to each shifting operation; whereby the output of said adder is the convolution of said first and second functions.
Claim 11
Independent Claim
135 words
A method of computing the correlation of first and second discrete functions comprising the step of: storing a series of charge signals representative of said first function in time reversed order in an array of photosensors; transferring a first set of said charge signals to a first CCD shift register and a second set of said charge signals to a second CCD shift register in accordance with a predetermined sequence of timing pulses representative of said second function; shifting said first and second CCD shift registers in accordance with a predetermined series of clock pulses; subtracting in an adder theoutput of said second CCD shift register from thhe output of said first CCD shift register subsequent to each shifting operation; whereby the output of said adder is the correlation of said first and second functions.
Claim 12
Independent Claim
135 words
A method of computing the correlation of first and second discrete functions comprising the step of: storing a series of charge signals representative of said first function in time reversed order in an array of photosensors; transferring a first set of said charge signals to a first CCD shift register and a second set of said charge signals to a second CCD shift register in accordance with a predetermined sequence of timing pulses representative of said second function; shifting said first and second CCD shift registers in accordance with a predetermined series of clock pulses; subtracting in an adder theoutput of said second CCD shift register from thhe output of said first CCD shift register subsequent to each shifting operation; whereby the output of said adder is the correlation of said first and second functions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-02-23 | 1979-08-25 | 1980-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-02-23 | 1983-08-25 | 1984-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-02-23 | 1987-08-25 | 1988-02-24 | $7700.00 | Window Closed / Lapsed |