US3819953A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Differential bucket-brigade circuit
Assignee: General Electric Co
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Filing: 1972-11-22
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Granted: 1974-06-25
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Expires: 1992-11-22
Abstract
Abstract A pair of bucket-brigade delay lines have equal numbers of bucket-brigade stages, and corresponding stages are clocked in parallel and in-phase. The analog input signal to the circuit is applied to a differential driver for inverting the analog input signal to one of the delay lines relative to the other delay line. The outputs of the delay lines are differentially summed and result in an output waveform which is a sampled and delayed version of the analog input signal with cancellation of D.C. and clock frequency components that are normally introduced in bucket-brigade delay line circuits.
Inventors
- 👤 Puckette C Mcd
- 👤 W Butler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:22
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/04
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
242 words
A digitally controlled analog charge transfer circuit comprising a first digitally controlled analog charge transfer circuit for sampling and delaying an analog input signal applied thereto, a second digitally controlled analog charge transfer circuit having the same number of charge transfer stages as said first charge transfer circuit for sampling and delaying by an equal time the analog input signal applied thereto but inverted with respect to the corresponding analog input signal applied to said first charge transfer circuit, first means connected to an input of said second charge transfer circuit for inverting the analog input signal applied thereto, clock pulse generator means for supplying two-phase clock voltage pulses in parallel and in-phase to corresponding switching elements of said first and second charge transfer circuits to cause propagation of the sampled analog input siGnal through said first and second charge transfer circuits, respectively, bias voltage means for biasing the inputs of said first and second charge transfer circuits sufficiently to prevent the sampled analog signal from forward biasing diode junctions within said first and second charge transfer circuits during its propagation through said first and second charge transfer circuits, and means for differentially summing outputs of said first and second charge transfer circuits to thereby cancel undesired D.C. and clock frequency voltage components in the signals at the outputs of said first and second charge transfer circuits resulting from the bias voltage and sample and delay processing of the analog input signal.
Claim 2
Dependent Claim
242 words
A digitally controlled analog charge transfer circuit comprising a first digitally controlled analog charge transfer circuit for sampling and delaying an analog input signal applied thereto, a second digitally controlled analog charge transfer circuit having the same number of charge transfer stages as said first charge transfer circuit for sampling and delaying by an equal time the analog input signal applied thereto but inverted with respect to the corresponding analog input signal applied to said first charge transfer circuit, first means connected to an input of said second charge transfer circuit for inverting the analog input signal applied thereto, clock pulse generator means for supplying two-phase clock voltage pulses in parallel and in-phase to corresponding switching elements of said first and second charge transfer circuits to cause propagation of the sampled analog input siGnal through said first and second charge transfer circuits, respectively, bias voltage means for biasing the inputs of said first and second charge transfer circuits sufficiently to prevent the sampled analog signal from forward biasing diode junctions within said first and second charge transfer circuits during its propagation through said first and second charge transfer circuits, and means for differentially summing outputs of said first and second charge transfer circuits to thereby cancel undesired D.C. and clock frequency voltage components in the signals at the outputs of said first and second charge transfer circuits resulting from the bias voltage and sample and delay processing of the analog input signal.
Claim 3
Dependent Claim
38 words
The digitally controlled analog charge transfer circuit set forth in claim 1 wherein said differential summing means is a differential summer having first and second inputs connected to outputs of said first and second charge transfer circuits, respectively.
Claim 4
Dependent Claim
29 words
The digitally controlled analog charge transfer circuit set forth in claim 2 wherein the first and second inputs of said differential summer are positive and negative input terminals thereof.
Claim 5
Dependent Claim
70 words
The digitally controlled analog charge transfer circuit set forth in claim 1 wherein said differential summing means comprises second means connected to an output of said second charge transfer circuit for inverting the sampled and delayed output signal thereof, and an algebraic summer having a first input connected to an output of said second inverting means and a second input connected to an output of said first charge transfer circuit.
Claim 6
Dependent Claim
45 words
The digitally controlled analog charge transfer circuit set forth in claim 1 and further comprising means connected to said first and second charge transfer circuits for cancelling undesired high frequency components in the signals at the outputs of said first and second charge transfer circuits.
Claim 7
Dependent Claim
62 words
The digitally controlled analog charge transfer circuit set forth in claim 5 wherein said high frequency cancelling means comprises a third digitally controlled analog charge transfer circuit connected in parallel with said first charge transfer circuit in push-pull relationship therewith, and a fourth digitally controlled analog charge transfer circuit connected in parallel with said second charge transfer circuit in push-pull relationship therewith.
Claim 8
Dependent Claim
103 words
The digitally controlled analog charge transfer circuit set forth in claim 6 wherein said third and fourth charge transfer circuits having the same number of charge transfer stages as said first charge transfer circuit, said clock pulse generator means supplying the two-phase clock voltage pulses in parallel to corresponding switching elements of said first, second, third, and fourth charge transfer circuits, the clock pulses supplied to corresponding switching elements of said first and third charge transfer circuits being in 180* out-of-phase relationship, the clock pulses supplied to corresponding switching elements of said second and fourth charge transfer circuits being in 180* out-of-phase relationship.
Claim 9
Dependent Claim
174 words
The digitally controlled analog charge transfer circuit set forth in claim 5 wherein said high frequency cancelling means comprises a first transistor having a gate electrode connected to an input of the last charge transfer stage of said first charge transfer circuit, and a drain electrode connected to a source of D.C. voltage, a first algebraic summer having a first input connected to the output of said first charge transfer circuit, said first transistor having a source electrode connected to a second input of said first algebraic summer, a second transistor having a gate electrode connected to an input of the last charge transfer stage of said second charge transfer circuit, and a drain electrode connected to the source of D.C. voltage, and a second algebraic summer having a first input connected tO the output of said second charge transfer circuit, said second transistor having a source electrode connected to a second input of said second algebraic summer, outputs of said first and second algebraic summers connected to inputs of said differentially summing means.
Claim 10
Dependent Claim
55 words
The digitally controlled analog charge transfer circuit set forth in claim 1 wherein said first and second charge transfer circuits are respectively first and second bucket-brigade delay lines each comprising an input sampling stage, a like plurality of delay line stages each consisting of a pair of serially connected bucket-brigade stages, and an output stage.
Claim 11
Dependent Claim
36 words
The digitally controlled analog charge transfer circuit set forth in claim 9 wherein each pair of serially connected bucket-brigade stages includes two serially connected electronic switches and a storage capacitor connected to each said electronic switch.
Claim 12
Dependent Claim
18 words
The digitally controlled analog charge transfer circuit set forth in claim 10 wherein said electronic switches are transistors.
Claim 13
Dependent Claim
21 words
The digitally controlled analog charge transfer circuit set forth in claim 11 wherein said transistor switches are of the bipolar type.
Claim 14
Dependent Claim
22 words
The digitally controlled analog charge transfer circuit set forth in claim 11 wherein said transistor switches are of the field effect type.
Claim 15
Dependent Claim
22 words
The digitally controlled analog charge transfer circuit set forth in claim 8 wherein said field effect transistors are of the MOSFET type.
Claim 16
Dependent Claim
22 words
The digitally controlled analog charge transfer circuit set forth in claim 13 wherein said field effect transistors are of the MESFET type.
Claim 17
Dependent Claim
22 words
The digitally controlled analog charge transfer circuit set forth in claim 13 wherein said field effect transistors are of the JFET type.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-24 | 1977-12-24 | 1978-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-24 | 1981-12-24 | 1982-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-24 | 1985-12-24 | 1986-06-25 | $7700.00 | Window Closed / Lapsed |