Parallel-serial converter

Claim 1

A parallel-serial converter which comprises a plurality of cascade connected selection-delay unit circuits, each of which delays a signal selected from a plurality of input signals, and which converts parallel input signals into serial signals, said selection-delay unit circuit comprising: a first transfer gate which receives a parallel signal and whose control gate is supplied with a first clock signal; a second transfer gate which receives an output signal from the immediately preceding selection-delay unit circuit, and whose control gate is supplied with a second clock signal; a first inverter which receives output signals from said first and second transfer gates; a third transfer gate which receives an output signal from said first inverter and whose control gate is supplied with a third clock signal; and a second inverter which receives an output signal from said third transfer gate and sends forth an output signal to the second transfer gate of the immediately succeeding selection-delay unit circuit; said first clock signal having a phase opposite to that of said third clock signal, and being supplied to the control gate of said first transfer gate only during the load mode in which a parallel signal is supplied to the selection-delay unit circuit; and said second clock signal having a phase opposite to that of said third clock signal, and being supplied to the control gate of said second transfer gate only during the shift mode in which the previously supplied parallel signal is shifted.