Patent BE529739A successfully refreshed from Google Patents.
US3619642A
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Multiphase binary shift register
Assignee: Texas Instruments Inc
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Filing: 1969-11-12
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Granted: 1971-11-09
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Expires: 1989-11-12
Abstract
Abstract A high stability, binary data, multiphase shift register of at least three phases, stores and shifts ''''N'''' bits of binary information in approximately (N X n)/(n-1) binary switches, where n is the number of phases utilized in the register, and N is the maximum number of bits capable of being stored in the shift register at all times during its operation. The binary switches are connected in series and each is then selectively connected to one of the n phases.
Inventors
- 👤 Roger S Dunn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:37
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28; G11C19/18; G11C19/182; G11C19/184
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
81 words
An N-bit binary data n-phase shift register where n is greater than 2, comprising: a. means for producing electrical pulses of n different phases; b. (N X n)/(n-1) binary switches connected in series for storing and shifting N bits of binary data; and c. means coupling each of n displaced groups of said binary switches selectively to said pulses of n different phases for selectively switching each group of said binary switches in response to pulses of a different respective phase.
Claim 2
Dependent Claim
81 words
An N-bit binary data n-phase shift register where n is greater than 2, comprising: a. means for producing electrical pulses of n different phases; b. (N X n)/(n-1) binary switches connected in series for storing and shifting N bits of binary data; and c. means coupling each of n displaced groups of said binary switches selectively to said pulses of n different phases for selectively switching each group of said binary switches in response to pulses of a different respective phase.
Claim 3
Dependent Claim
110 words
An N-bit binary data n-phase shift register where n is greater than 2, comprising: a. means for producing electrical pulses of n different phases; b. (N X n)/(n-1) binary switches connected in series for storing and shifting N bits of binary data; and c. means coupling every nth binary switch beginning with the first binary switch to pulses of one of said n phases and every nth binary switch beginning with the second binary switch progressively through the nth binary switch selectively to the pulses of the remaining phases for selectively switching each of n displaced groups of said binary switches in response to pulses of a different respective phase.
Claim 4
Dependent Claim
110 words
An N-bit binary data n-phase shift register where n is greater than 2, comprising: a. means for producing electrical pulses of n different phases; b. (N X n)/(n-1) binary switches connected in series for storing and shifting N bits of binary data; and c. means coupling every nth binary switch beginning with the first binary switch to pulses of one of said n phases and every nth binary switch beginning with the second binary switch progressively through the nth binary switch selectively to the pulses of the remaining phases for selectively switching each of n displaced groups of said binary switches in response to pulses of a different respective phase.
Claim 5
Dependent Claim
89 words
An N-bit high stability binary data three-phase shift register which comprises: clock means for producing electrical pulses of three different phases; 3N/2 binary switches for storing and shifting N bits of binary data; means electrically connecting the binary switches in series; means electrically connecting every third binary switch beginning with the second switch to the first phase; means electrically connecting every third binary switch beginning with the first switch to the second phase; means electrically connecting every third binary switch beginning with the third switch to the third phase.
Claim 6
Dependent Claim
89 words
An N-bit high stability binary data three-phase shift register which comprises: clock means for producing electrical pulses of three different phases; 3N/2 binary switches for storing and shifting N bits of binary data; means electrically connecting the binary switches in series; means electrically connecting every third binary switch beginning with the second switch to the first phase; means electrically connecting every third binary switch beginning with the first switch to the second phase; means electrically connecting every third binary switch beginning with the third switch to the third phase.
Claim 7
Dependent Claim
19 words
The three-phase shift register described in claim 3 wherein the binary switches are metal-insulator-semiconductor field effect transistor delay switches.
Claim 8
Dependent Claim
15 words
The three-phase shift register described in claim 3 wherein the binary switches are bistable flip-flops.
Claim 9
Dependent Claim
106 words
An N-bit high stability binary data four-phase shift register which comprises: clock means for producing electrical pulses of four different phases; 4N/3 binary switches for storing and shiftIng N bits of binary data; electrical means for connecting the switches in series; means electrically connecting every fourth binary switch beginning with the second switch to the first phase; means electrically connecting every fourth binary switch beginning with the first switch to the second phase; means electrically connecting every fourth binary switch beginning with the fourth switch to the third phase; and means electrically connecting every fourth binary switch beginning with the third switch to the fourth phase.
Claim 10
Dependent Claim
106 words
An N-bit high stability binary data four-phase shift register which comprises: clock means for producing electrical pulses of four different phases; 4N/3 binary switches for storing and shiftIng N bits of binary data; electrical means for connecting the switches in series; means electrically connecting every fourth binary switch beginning with the second switch to the first phase; means electrically connecting every fourth binary switch beginning with the first switch to the second phase; means electrically connecting every fourth binary switch beginning with the fourth switch to the third phase; and means electrically connecting every fourth binary switch beginning with the third switch to the fourth phase.
Claim 11
Dependent Claim
19 words
The four-phase shift register described in claim 6 wherein the binary switches are metal-insulator-semiconductor field effect transistor delay switches.
Claim 12
Dependent Claim
15 words
The four-phase shift register described in claim 6 wherein the binary switches are bistable flip-flops.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-08 | 1975-05-10 | 1975-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-08 | 1979-05-10 | 1979-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-08 | 1983-05-10 | 1983-11-09 | $7700.00 | Window Closed / Lapsed |