US3708690A
Expired / Lapsed
US
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Shift register
Assignee: Mos Technology Inc
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Filing: 1971-02-22
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Granted: 1973-01-02
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Expires: 1991-02-22
Abstract
Abstract A multi-phase shift register having a plurality of parallel columns each comprising n stages, where n is preferably greater than 3, and where the data is advanced along each such column by first shifting the data from its nth stage to the column output terminal, then from the preceding stage to the nth stage, and then from each of the next preceding stages sequentially to their succeeding stages, until the first stage of the column is reached, whereupon the first stage is emptied of data and free to receive new input data. The advance sequence of the parallel columns is synchronized with the application of the input data, and this sequence is constantly repeated, so that successive input bits of data are directed to different respective columns of the shift register, and then along these columns to their common output terminal, where the pulses are recombined to form the original input pulse series. In one embodiment the advance sequence is delayed one clock pulse in each successive column, so that each column delivers an output pulse, and is ready to receive new input data, one clock pulse behind the preceding column. In another embodiment, successive n bits of data are delayed relative to one another and applied simultaneously to different first stages of n parallel columns, and then are advanced along the column simultaneously with the same advance sequence. At the output of the columns, the bits of data are again delayed and recombined to form the original time sequence series. Several of these multi-phase shift registers are generally connected in cascade, and the advance sequences of the cascaded registers synchronized, so that a large number of data bits may be stored and shifted along the respective columns of the register.
Inventors
- 👤 J Paivinen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 02:26
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/08; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/184
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
265 words
A multi-phase shift register comprising a plurality of shift register channels arranged in parallel, each such channel having an input and an output terminal and including n data storage circuits connected serially between said terminals in the sequence of one to n, where n is greater than 3, each channel being capable of storing n-1 bits of data, a shift terminal connected to each such data storage circuit, input means for applying input data bits in the form of electrical signals to the respective input terminals of said channels, means for advancing successive ones of said data bits along different ones of said parallel channels, with the first data bit being advanced along a first such channel and Each following data bit being advanced along a different channel, to continuously advance successive data bits along different ones of the parallel channels according to a predetermined distribution pattern, and then repeating said pattern, said advancing means including switching means for applying shift signals sequentially to the shift terminals of the storage circuits in each channel in the sequence of circuit n, circuit n-1, and so forth to circuit one, and then repeating such sequence, an output circuit connected to the nth circuit of each of said channels, and means for synchronizing the receipt of data bits from said input means, and the delivery of data bits to said output circuit, with the advancement of the data bits along said channels to cause at least one data bit to be received and at least one to be delivered with each advancement of data bits along the channels.
Claim 2
Dependent Claim
265 words
A multi-phase shift register comprising a plurality of shift register channels arranged in parallel, each such channel having an input and an output terminal and including n data storage circuits connected serially between said terminals in the sequence of one to n, where n is greater than 3, each channel being capable of storing n-1 bits of data, a shift terminal connected to each such data storage circuit, input means for applying input data bits in the form of electrical signals to the respective input terminals of said channels, means for advancing successive ones of said data bits along different ones of said parallel channels, with the first data bit being advanced along a first such channel and Each following data bit being advanced along a different channel, to continuously advance successive data bits along different ones of the parallel channels according to a predetermined distribution pattern, and then repeating said pattern, said advancing means including switching means for applying shift signals sequentially to the shift terminals of the storage circuits in each channel in the sequence of circuit n, circuit n-1, and so forth to circuit one, and then repeating such sequence, an output circuit connected to the nth circuit of each of said channels, and means for synchronizing the receipt of data bits from said input means, and the delivery of data bits to said output circuit, with the advancement of the data bits along said channels to cause at least one data bit to be received and at least one to be delivered with each advancement of data bits along the channels.
Claim 3
Dependent Claim
19 words
A shift register as in claim 1 having at least three, and more than n/2, parallel shift register channels.
Claim 4
Dependent Claim
13 words
A shift register as in claim 1 having n parallel shift register channels.
Claim 5
Dependent Claim
67 words
A shift register as in claim 1, wherein the means for advancing data includes means for staggering the advancement of the data in the different parallel channels such that in each such channel the data is being advanced from its nth circuit to the output terminal of the channel while in a different channel the data is being advanced from the n-1 circuit to the nth circuit.
Claim 6
Dependent Claim
63 words
A shift register as in claim 4, wherein the shift terminals of the circuits of the different parallel channels are interconnected, with the shift terminal of the nth circuit of each such channel being connected to the shift terminal of the n-1 circuit of a different channel and to the shift terminal of the next lower order circuit of each successive channel thereafter.
Claim 7
Dependent Claim
22 words
A shift register as in claim 4, wherein the input terminals of the respective shift register channels are connected electrically in common.
Claim 8
Dependent Claim
54 words
A shift register as in claim 4, further including a plurality of gate circuits, each having an input and an output terminal, with the output terminals thereof connected in common and the input terminals connected to the respective output terminals of the parallel shift register channels, and means for energizing said gate circuits sequentially.
Claim 9
Dependent Claim
66 words
A shift register as in claim 7, wherein the input terminals of the respective shift register channels are connected in common, further including a recirculating path between said common input terminals and the common output terminals of said gate circuits, an additional gate circuit in said recirculating path, and means for selectively energizing said additional gate circuit to effect data recirculation through said shift register channels.
Claim 10
Dependent Claim
58 words
A shift register as in claim 1, wherein the means for advancing data includes means for synchronizing the advancement of the data in said parallel channels such that the data in the nth circuits of all of said channels is advanced simultaneously and the data in each successive lower order circuit is likewise advanced simultaneously in all channels.
Claim 11
Dependent Claim
41 words
A shift register as in claim 9, wherein the shift terminals of the nth circuits of all of the parallel channels are interconnected and the shift terminals of the respective lower order circuits of all of the channels are likewise interconnected.
Claim 12
Dependent Claim
42 words
A shift register as in claim 9, wherein the means for applying input data bits includes means for grouping said data bits and means for inserting said grouped data bits simultaneously into the first circuits of the respective parallel shift register channels.
Claim 13
Dependent Claim
52 words
A shift register as in claim 11, wherein said means for applying input data bits includes means for receiving a series of the data bits sequentially and delaying the bits with respect to each other and inserting such delayed Bits simultaneously into the first circuits of the respective parallel shift register channels.
Claim 14
Dependent Claim
32 words
A shift register as in claim 12, wherein said means for delaying a series of data bits includes storage circuits connected to the respective input terminals of the parallel shift register channels.
Claim 15
Dependent Claim
54 words
A shift register as in claim 13, further including means for synchronizing the storage of data in said storage circuits with the advancement of the data along the channels such that the storage circuits are all filled with data bits when the data has been advanced out of the first circuit of each channel.
Claim 16
Dependent Claim
44 words
A shift register as in claim 9, further including means for storing the data bits simultaneously advanced from the nth circuits of substantially all of said parallel channels, and means for sequentially advancing said data bits from said storage means to an output terminal.
Claim 17
Dependent Claim
32 words
A shift register as in claim 15, further including means for synchronizing the sequential advance of said data bits from said storage means with the advancement of data along said parallel channels.
Claim 18
Dependent Claim
70 words
A shift register as in claim 16, wherein said synchronizing means causes one data bit to be advanced from said storage means with each advancement of the data along the parallel channels, and wherein all of the data bits in the storage means are advanced by the time of the next advancement of data bits simultaneously from the nth circuits of all of the parallel channels into the storage means.
Claim 19
Dependent Claim
75 words
A shift register as in claim 9, wherein the shift terminals of the nth circuits of all of the parallel channels are interconnected by a straight conductor, the shift terminals of the n-1 circuits of all channels are interconnected by a second straight conductor substantially parallel to the first, and each of the remaining circuits of like order of the respective channels are interconnected by a straight conductor substantially parallel to the first and second.
Claim 20
Dependent Claim
151 words
A multi-phase shift register comprising a plurality of n shift register channels arranged in parallel, where n is greater than 2, each such channel having an input and an output terminal and including n data storage circuits connected serially between said terminals in the sequence of one to n, each channel being capable of storing n-1 bits of data, a shift terminal connected to each such data storage circuit, input means for applying input data bits in the form of electrical signals to the respective input terminals of said channels, and means for advancing successive ones of said data bits along different ones of said parallel channels, simultaneously and synchronously, said advancing means including switching means for applying shift signals sequentially to the shift terminals of the storage circuits in each channel in the sequence of circuit n, circuit n-1, and so forth to circuit one, and then repeating such sequence.
Claim 21
Dependent Claim
151 words
A multi-phase shift register comprising a plurality of n shift register channels arranged in parallel, where n is greater than 2, each such channel having an input and an output terminal and including n data storage circuits connected serially between said terminals in the sequence of one to n, each channel being capable of storing n-1 bits of data, a shift terminal connected to each such data storage circuit, input means for applying input data bits in the form of electrical signals to the respective input terminals of said channels, and means for advancing successive ones of said data bits along different ones of said parallel channels, simultaneously and synchronously, said advancing means including switching means for applying shift signals sequentially to the shift terminals of the storage circuits in each channel in the sequence of circuit n, circuit n-1, and so forth to circuit one, and then repeating such sequence.
Claim 22
Dependent Claim
178 words
A multi-phase shift register as in claim 19, wherein said input means includes means for receiving data bits one after another and for distributing said data bits to said n parallel channels one after the other, so that the successive data bits pass to different parallel channels until all n channels have received a data bit and the distribution sequence is then repeated, further including an output circuit means for receiving data bits from the nth circuits of all of said parallel channels, one channel after the other until a data bit has been received from all n channels, and for delivering said data bits to a common terminal, one data bit after the other, in the same sequence as they were received by said distributing means, and means for synchronizing said input means and said output means with the advancement of the data bits along said channels so that one data bit is received from said input means and one data bit is delivered by said output means with each advancement of data bits along the channels.
Claim 23
Dependent Claim
40 words
A multi-phase shift register as in claim 19, wherein said advancing means constitutes means for applying a first pulse to all of the storage circuits of each channel and a second pulse to only one storage circuit in each channel.
Claim 24
Dependent Claim
45 words
A multi-phase shift register as in claim 19, wherein said data storage circuits each contain just a single storage location which represents a binary data bit of either ''''1'''' or ''''0'''' significance, the data bit being stored as either a high or low voltage level.
Claim 25
Dependent Claim
64 words
A multi-phase shift register as in claim 19, wherein each storage circuit is binary in character and delivers a data bit of binary significance ''''1'''' to the succeeding storage circuit, or to an output terminal in the case of the nth circuits, only if it is in a particular one of its binary states, and not if it is in its other binary state.
Claim 26
Dependent Claim
150 words
A multi-phase shift register comprising a plurality of n shift register channels arranged in parallel, where n is greater than 3, each such channel having an input and an output terminal and including at least n data storage circuits connected serially between said terminals in the sequence of one to n, each channel being capable of storing at least n-1 bits of data, a shift terminal connected to each such data storage circuit, input means for applying input data bits in the form of electrical signals to the respective input terminals of said channels, and means for advancing said data bits along different ones of said parallel channels, said advancing means including control means for applying n shift signals sequentially to the shift terminals of the storage circuits in each channel in the sequence of circuit n, circuit n-1, and so forth to circuit one, and then repeating such sequence.
Claim 27
Dependent Claim
150 words
A multi-phase shift register comprising a plurality of n shift register channels arranged in parallel, where n is greater than 3, each such channel having an input and an output terminal and including at least n data storage circuits connected serially between said terminals in the sequence of one to n, each channel being capable of storing at least n-1 bits of data, a shift terminal connected to each such data storage circuit, input means for applying input data bits in the form of electrical signals to the respective input terminals of said channels, and means for advancing said data bits along different ones of said parallel channels, said advancing means including control means for applying n shift signals sequentially to the shift terminals of the storage circuits in each channel in the sequence of circuit n, circuit n-1, and so forth to circuit one, and then repeating such sequence.
Claim 28
Dependent Claim
106 words
A multi-phase shift register as in claim 24, wherein the input means includes means for receiving a series string of data bits in a predetermined sequence and distributing said data bits to different ones of said n parallel channels, so that every nth bit passes along the same channel but all other bits pass along different channels, and further including an output circuit for receiving data bits from the nth stages of all of said parallel channels and recombining said data bits into a series string of bits in said predetermined sequence, said distributor means and output circuit means operating under control of said control means.
Claim 29
Dependent Claim
50 words
A multi-phase shift register as in claim 25, wherein the control means includes means for synchronizing the input means and output circuit with the advancement of data bits along the channels to deliver one data bit from the output circuit with each advance of the data bits along the channels.
Claim 30
Dependent Claim
271 words
A multi-phase shift register comprising a plurality of shift register sections arranged in series, with the output of each except the last being connected to the input of the next, each such section including a plurality of shift register channels arranged in parallel, each channel having an input and an output terminal and including n data storage circuits connected serially between said terminals in the sequence of one to n, where n is greater than 3, each channel being capable of storing n-1 bits of data, circuit means connecting the output terminals of the respective channels of each such section to the input terminals of the channels of the next succeeding section of the series, to connect the corresponding channels of the succeeding sections in series, a shift terminal connected to each such data storage circuit, circuit means connecting in common the corresponding shift terminals of the serially connected channels of the successive sections, input means for applying input data bits in the form of electrical signals to the respectiVe input terminals of the channels of the first such section, means for advancing successive ones of said data bits along different ones of said parallel channels of said first section and then along the corresponding channels of each succeeding section, said advancing means including switching means for applying shift signals sequentially to the shift terminals of the storage circuits in each section to advance the data bits through each such section in sequence, said signals being applied to the circuits in each channel in the sequence of circuit n, circuit n-1, and so forth to circuit one, and then being repeated.
Claim 31
Dependent Claim
271 words
A multi-phase shift register comprising a plurality of shift register sections arranged in series, with the output of each except the last being connected to the input of the next, each such section including a plurality of shift register channels arranged in parallel, each channel having an input and an output terminal and including n data storage circuits connected serially between said terminals in the sequence of one to n, where n is greater than 3, each channel being capable of storing n-1 bits of data, circuit means connecting the output terminals of the respective channels of each such section to the input terminals of the channels of the next succeeding section of the series, to connect the corresponding channels of the succeeding sections in series, a shift terminal connected to each such data storage circuit, circuit means connecting in common the corresponding shift terminals of the serially connected channels of the successive sections, input means for applying input data bits in the form of electrical signals to the respectiVe input terminals of the channels of the first such section, means for advancing successive ones of said data bits along different ones of said parallel channels of said first section and then along the corresponding channels of each succeeding section, said advancing means including switching means for applying shift signals sequentially to the shift terminals of the storage circuits in each section to advance the data bits through each such section in sequence, said signals being applied to the circuits in each channel in the sequence of circuit n, circuit n-1, and so forth to circuit one, and then being repeated.
Claim 32
Dependent Claim
15 words
A multi-phase shift register as in claim 27, wherein each section includes n parallel channels.
Claim 33
Dependent Claim
72 words
A multi-phase shift register as in claim 27, wherein the means for advancing data includes means for staggering the advancement of the data in the different parallel channels of each section such that in each such channel the data is being advanced from its nth circuit to the output terminal of the channel while in a different channel the data is being advanced from the n-1 circuit to the nth circuit thereof.
Claim 34
Dependent Claim
65 words
A multi-phase shift register as in claim 29, wherein the shift terminals are interconnected, with the shift terminal of the nth circuit of each channel of one such section being connected to the shift terminal of the n-1 circuit of a different channel of the same section and to the shift terminal of the next lower order circuit of each successive channel of such section.
Claim 35
Dependent Claim
39 words
A multi-phase shift register as in claim 29, wherein the input means includes means for inserting said data bits sequentially into said channels, one channel after the other, in synchronism with the advancement of the data along the sections.
Claim 36
Dependent Claim
80 words
A multi-phase shift register as in claim 27, wherein said input means includes means for receiving a series of the data bits sequentially and delaying the bits with respect to each other and inserting such delayed bits simultaneously into the first circuits of the respective channels of the first section, and further including means for synchronizing said input means with the advancement of data along said channels to receive a data bit with each advancement of data along a channel.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-02 | 1976-07-03 | 1977-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-02 | 1980-07-03 | 1981-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-02 | 1984-07-03 | 1985-01-02 | $7700.00 | Window Closed / Lapsed |