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US4378629A
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Semiconductor embedded layer technology including permeable base transistor, fabrication method
Assignee: Massachusetts Institute of Technology
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Filing: 1979-08-10
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Granted: 1983-04-05
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Expires: 1999-08-10
Abstract
Abstract A layer of material such as the metal base of a transistor is embedded in single crystal. A layer of the material with small, uniformly dimensioned and uniformly spaced openings is formed on a single crystal substrate, and the single crystal is grown from the exposed portions of the substrate over the layer of material. For best results, the layer of material to be embedded is deposited relative to the crystal orientation to provide a much greater rate of crystal growth laterally across the layer than away from the crystal substrate. The method is particularly useful in fabricating a permeable base transistor having slits formed in the metal base layer. An integrated circuit can be fabricated by forming a pattern of conductive material on a single crystal, that pattern having continuous regions which inhibit further crystal growth and narrow regions or regions having openings therein which permit lateral crystal growth across those regions. In that way, the conductive pattern is selectively embedded with the continuous regions left exposed after crystal growth. Connections can be made between the exposed regions and a pattern on the new crystal layer. This method has particular usefulness in fabricating multi-level integrated circuits.
Inventors
- 👤 Carl O. Bozler
- 👤 Gary D. Alley
- 👤 William T. Lindley
- 👤 R. Allen Murphy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:07
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/012; H10D1/00; H10D1/60; H10D1/68; H10D30/202; H10P; H10P14/00; H10P14/20; H10P14/27; H10P14/271; H10P14/29; H10P14/2901; H10P14/2907; H10P14/2911; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/3414; H10P14/3421; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/20; H10W20/40; H10W20/482; H10W20/484; H10W72/00; Y; Y10; Y10S; Y10S148/00; Y10S148/164
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
130 words
A method of fabricating a transistor device of the type comprising a single type of semiconductor material divided into emitter and collector regions by a metal base layer, the method comprising: growing a single semiconductor crystal to form a first emitter or collector region of the transistor; providing a Schottky barrier metal base layer on a surface of the crystal, the thickness of the metal base layer being in the order of 10% of the zero bias depletion width in the semiconductor, the metal base layer having slits therein of a width in the order of the zero bias depletion width of the semiconductor; and growing a single semiconductor crystal from the first region over the metal base layer to provide a second collector or emitter region of the transistor.
Claim 2
Independent Claim
130 words
A method of fabricating a transistor device of the type comprising a single type of semiconductor material divided into emitter and collector regions by a metal base layer, the method comprising: growing a single semiconductor crystal to form a first emitter or collector region of the transistor; providing a Schottky barrier metal base layer on a surface of the crystal, the thickness of the metal base layer being in the order of 10% of the zero bias depletion width in the semiconductor, the metal base layer having slits therein of a width in the order of the zero bias depletion width of the semiconductor; and growing a single semiconductor crystal from the first region over the metal base layer to provide a second collector or emitter region of the transistor.
Claim 3
Dependent Claim
62 words
A method of fabricating a transistor device as claimed in claim 1 wherein the metal base layer is provided by forming a striated relief structure on a semiconductor surface, and coating both sides of ridges of the relief structure by a directed metal deposition, the transverse dimension of the deposition on each ridge being limited by the shadow of an adjacent ridge.
Claim 4
Dependent Claim
60 words
A method of fabricating a transistor device as claimed in claim 1 wherein the single semiconductor crystal is grown from the first region over the metal base layer by depositing an amorphous or polycrystalline layer over the metal base layer and scanning that layer with an electromagnetic beam to recrystallize the layer as a single crystal from the first region.
Claim 5
Dependent Claim
22 words
A method of fabricating a transistor device as claimed in claim 1 wherein the second region is grown by vapor phase epitaxy.
Claim 6
Independent Claim
142 words
A method of fabricating a transistor device of the type comprising a single type of semiconductor material divided into emitter and collector regions by a metal base layer, the method comprising: growing a single semiconductor crystal to form a first emitter or collector region of the transistor; providing a Schottky barrier metal base layer on a surface of the crystal the thickness of the metal base layer being in the order of 10% of the zero bias depletion width in the semiconductor; removing portions of the metal base layer to provide openings therein to expose the underlying semiconductor crystal the openings having a width in the order of the zero bias depletion width of the semiconductor; and growing a single semiconductor crystal from the first region over the metal base layer to provide a second collector or emitter region of the transistor.
Claim 7
Independent Claim
142 words
A method of fabricating a transistor device of the type comprising a single type of semiconductor material divided into emitter and collector regions by a metal base layer, the method comprising: growing a single semiconductor crystal to form a first emitter or collector region of the transistor; providing a Schottky barrier metal base layer on a surface of the crystal the thickness of the metal base layer being in the order of 10% of the zero bias depletion width in the semiconductor; removing portions of the metal base layer to provide openings therein to expose the underlying semiconductor crystal the openings having a width in the order of the zero bias depletion width of the semiconductor; and growing a single semiconductor crystal from the first region over the metal base layer to provide a second collector or emitter region of the transistor.
Claim 8
Dependent Claim
26 words
A method of fabricating a transistor device as claimed in claim 5 wherein the removed portions of the metal base layer form slits in that layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-04 | 1986-10-04 | 1987-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-04 | 1990-10-04 | 1991-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-04 | 1994-10-04 | 1995-04-05 | $7700.00 | Window Closed / Lapsed |