← Back to Patent Explorer
US3401449A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of fabricating a metal base transistor

Assignee: Texas Instruments Inc
•
Filing: 1965-10-24
•
Granted: 1968-09-17
•
Expires: 1985-10-24
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

No abstract record available.

Inventors

  • 👤 Don W Shaw

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 22:06
CPC Classifications
C; C30; C30B; C30B25/00; C30B25/02; C30B25/04; H; H10; H10D; H10D99/00; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/29; H10P14/2901; H10P14/2907; H10P14/2911; H10P14/32; H10P14/3202; H10P14/3214; H10P14/3221; H10P14/34; H10P14/3402; H10P14/3414; H10P14/3421; Y; Y10; Y10S; Y10S148/00; Y10S148/029; Y10S148/05; Y10S148/084; Y10S148/115; Y10S148/142

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 132 words
IN A METHOD OF FABRICATING A SEMICONDUCTOR DEVICE THE STEPS OF: (A) FORMING A FIRST LAYER OF SEMICONDUCTOR MATERIAL ADJACENT A SECOND LAYER OF SEMICONDUCTOR MATERIAL, SAID FIRST LAYER BEING OF SUBSTNATIALLY HIGHER ELECTRICAL RESISTIVITY THAN SAID SECOND LAYER, (B) SELECTIVELY REMOVING A PORTION OF SAID FIRST LAYER TO FORM A POCKET AND EXPOSE A SURFACE OF SAID SECOND LAYER AT THE BOTTOM OF SAID POCKET, THE REMAINING PORTIONS OF SAID POCKET BEING OF SAID HIGHER ELECTRICAL RESISTIVITY, (C) ELECTROPLATING A METAL LAYER WITHIN SAID POCKET UPON THE SAID EXPOSED SURFACE OF SAID SECOND LAYER, AND (D) EPITAXIALLY GROWING A THIRD REGION OF SEMICONDUCTOR MATERIAL OVER SAID METAL LAYER WITHIN SAID POCKET, SAID EPITAXIAL GROWTH PROCEEDING FROM THE SAID REMAINING PORTIONS OF SAID POCKET AND EXTENDING SUBSTANTIALLY LATERALLY OVER SAID METAL LAYER.
Claim 2
Dependent Claim 132 words
IN A METHOD OF FABRICATING A SEMICONDUCTOR DEVICE THE STEPS OF: (A) FORMING A FIRST LAYER OF SEMICONDUCTOR MATERIAL ADJACENT A SECOND LAYER OF SEMICONDUCTOR MATERIAL, SAID FIRST LAYER BEING OF SUBSTNATIALLY HIGHER ELECTRICAL RESISTIVITY THAN SAID SECOND LAYER, (B) SELECTIVELY REMOVING A PORTION OF SAID FIRST LAYER TO FORM A POCKET AND EXPOSE A SURFACE OF SAID SECOND LAYER AT THE BOTTOM OF SAID POCKET, THE REMAINING PORTIONS OF SAID POCKET BEING OF SAID HIGHER ELECTRICAL RESISTIVITY, (C) ELECTROPLATING A METAL LAYER WITHIN SAID POCKET UPON THE SAID EXPOSED SURFACE OF SAID SECOND LAYER, AND (D) EPITAXIALLY GROWING A THIRD REGION OF SEMICONDUCTOR MATERIAL OVER SAID METAL LAYER WITHIN SAID POCKET, SAID EPITAXIAL GROWTH PROCEEDING FROM THE SAID REMAINING PORTIONS OF SAID POCKET AND EXTENDING SUBSTANTIALLY LATERALLY OVER SAID METAL LAYER.

References Cited (Backward Citations)

US3096259A Cited
US3042565A Cited
US3185935A Cited
US3121809A Cited
US3328216A Cited
US3280391A Cited
US3349297A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1971-09-17 1972-03-18 1972-09-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1975-09-17 1976-03-18 1976-09-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1979-09-17 1980-03-18 1980-09-17 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag