Patent US4375124A successfully refreshed from Google Patents.
US4375124A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power static induction transistor fabrication
Assignee: Verizon Laboratories Inc
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Filing: 1981-11-12
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Granted: 1983-03-01
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Expires: 2001-11-12
Abstract
Abstract A method for fabricating a gate-source structure for a recessed-gate static induction transistor. The method is characterized by use of doped polysilicon to fill the recessed gate grooves after the gate grooves have been etched and diffused. The gate grooves have depth greater than width and therefore the surface of the polysilicon layer deposit is substantially planar. The planar surface allows photolithographic techniques to be used for formation of gate contact regions and for depositing of metal gate and source electrodes.
Inventors
- 👤 Adrian I. Cogan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:21
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D62/00; H10D62/10; H10D62/17; H10D62/343
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
175 words
A method for forming a gate-source structure for a recessed-gate static induction transistor, said method comprising the steps of: growing a high resistivity epitaxial silicon layer on a semiconductor substrate; growing a silicon dioxide layer over said epitaxial layer; etching parallel windows through said silicon dioxide layer at predetermined gate and source locations; masking said source windows and etching recessed gate grooves in said epitaxial layer, said gate grooves having depth substantially greater than width; removing said source window masking; depositing a doped polysilicon layer in said gate grooves, in said source windows and on said silicon dioxide layer, said deposit continuing until the surface of said polysilicon layer is substantially planar; removing said doped polysilicon layer to open said source windows and to form gate contact regions, said doped layer removal accomplished using relaxed registration photolithography; forming source regions in said epitaxial layer at source window locations; and depositing metal in said source window and over said gate contact regions to form gate and source electrodes, said metal depositing accomplished using relaxed registration photolithography.
Claim 2
Independent Claim
175 words
A method for forming a gate-source structure for a recessed-gate static induction transistor, said method comprising the steps of: growing a high resistivity epitaxial silicon layer on a semiconductor substrate; growing a silicon dioxide layer over said epitaxial layer; etching parallel windows through said silicon dioxide layer at predetermined gate and source locations; masking said source windows and etching recessed gate grooves in said epitaxial layer, said gate grooves having depth substantially greater than width; removing said source window masking; depositing a doped polysilicon layer in said gate grooves, in said source windows and on said silicon dioxide layer, said deposit continuing until the surface of said polysilicon layer is substantially planar; removing said doped polysilicon layer to open said source windows and to form gate contact regions, said doped layer removal accomplished using relaxed registration photolithography; forming source regions in said epitaxial layer at source window locations; and depositing metal in said source window and over said gate contact regions to form gate and source electrodes, said metal depositing accomplished using relaxed registration photolithography.
Claim 3
Dependent Claim
33 words
A method as defined in claim 1 in which impurities are diffused into said gate grooves after said etching to form said gate grooves and prior to said removing said source window masking.
Claim 4
Dependent Claim
42 words
A method as defined in claim 1 in which gate regions are formed adjacent said gate grooves by a drive-in diffusion step after said doped polysilicon layer is deposited and during which impurities from said polysilicon layers are used as a source.
Claim 5
Dependent Claim
19 words
A method as defined in claim 1 wherein the depth of said gate grooves is approximately twice the width.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-02-28 | 1986-08-30 | 1987-03-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-02-28 | 1990-08-30 | 1991-03-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-02-28 | 1994-08-30 | 1995-03-01 | $7700.00 | Window Closed / Lapsed |