US4333224A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating polysilicon/silicon junction field effect transistors
Assignee: Individual
•
Filing: 1980-05-06
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Granted: 1982-06-08
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Expires: 2000-05-06
Abstract
Abstract A junction field effect transistor is fabricated in crystalline silicon by using oppositely doped polysilicon as the gate (POSFET). The depletion region of the pn (or np) junction formed at the polysilicon/silicon interface is used as the gate electrode to modulate the current path through the silicon channel from source to drain, the source and drain contacts may either be conventional metal or polysilicon heavily doped of the same conductivity type as the single crystal silicon substrate.
Inventors
- 👤 Bobby L. Buchanan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:38
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/602; H10D30/00; H10D30/80; H10D30/83; H10D62/00; H10D62/10; H10D62/17; H10D62/343; Y; Y10; Y10S; Y10S148/00; Y10S148/053; Y10S148/088; Y10S148/122
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
118 words
The method of fabricating a junction field effect transistor comprising the steps of: fabricating a silicon epi wafer having a bounding n type silicon substrate and a p type silicon overlay substrate; thermally growing a layer of silicon dioxide on said overlay substrate; masking said layer of silicon dioxide to define a gate region; etching through said layer of silicon dioxide in the gate region to said overlay substrate; depositing heavily doped polysilicon into said etched gate region; masking said layer of silicon dioxide to define source and drain contact regions; etching through said layer of silicon dioxide in said source and drain regions to said overlay substrate; and evaporating aluminum contacts into said source and drain regions.
Claim 2
Independent Claim
118 words
The method of fabricating a junction field effect transistor comprising the steps of: fabricating a silicon epi wafer having a bounding n type silicon substrate and a p type silicon overlay substrate; thermally growing a layer of silicon dioxide on said overlay substrate; masking said layer of silicon dioxide to define a gate region; etching through said layer of silicon dioxide in the gate region to said overlay substrate; depositing heavily doped polysilicon into said etched gate region; masking said layer of silicon dioxide to define source and drain contact regions; etching through said layer of silicon dioxide in said source and drain regions to said overlay substrate; and evaporating aluminum contacts into said source and drain regions.
Claim 3
Independent Claim
201 words
The method of fabricating a junction field effect transistor comprising the steps of: fabricating a sapphire bounding substrate having an overlay substrate of p type silicon; growing a layer of undoped insulating polysilicon on said overlay substrate; growing a layer of silicon dioxide on said layer of undoped insulating polysilicon; masking said layer of silicon dioxide to define source and drain regions; etching through said layer of silicon dioxide in the source and drain regions to said undoped insulating polysilicon layer; heavily diffusing p type donors into the exposed source and drain regions of said undoped insulating polysilicon layer; growing a second layer of silicon dioxide over said silicon dioxide layer and said source and drain regions; masking said second layer of silicon dioxide to define a gate region; etching said second layer of silicon dioxide in the gate region through to said undoped insulating polysilicon layer; heavily diffusing n type donors into the exposed gate region of said undoped insulating polysilicon layer; masking said second layer of silicon dioxide to define source and drain regions; etching said second layer of silicon dioxide through to said undoped insulating polysilicon layer, and evaporating aluminum into said etched source, gate, and drain regions.
Claim 4
Independent Claim
201 words
The method of fabricating a junction field effect transistor comprising the steps of: fabricating a sapphire bounding substrate having an overlay substrate of p type silicon; growing a layer of undoped insulating polysilicon on said overlay substrate; growing a layer of silicon dioxide on said layer of undoped insulating polysilicon; masking said layer of silicon dioxide to define source and drain regions; etching through said layer of silicon dioxide in the source and drain regions to said undoped insulating polysilicon layer; heavily diffusing p type donors into the exposed source and drain regions of said undoped insulating polysilicon layer; growing a second layer of silicon dioxide over said silicon dioxide layer and said source and drain regions; masking said second layer of silicon dioxide to define a gate region; etching said second layer of silicon dioxide in the gate region through to said undoped insulating polysilicon layer; heavily diffusing n type donors into the exposed gate region of said undoped insulating polysilicon layer; masking said second layer of silicon dioxide to define source and drain regions; etching said second layer of silicon dioxide through to said undoped insulating polysilicon layer, and evaporating aluminum into said etched source, gate, and drain regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-06-07 | 1985-12-07 | 1986-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-06-07 | 1989-12-07 | 1990-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-06-07 | 1993-12-07 | 1994-06-08 | $7700.00 | Window Closed / Lapsed |