US4328611A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacture of an interdigitated collector structure utilizing etch and refill techniques
Assignee: Motorola Solutions Inc
•
Filing: 1980-04-28
•
Granted: 1982-05-11
•
Expires: 2000-04-28
Abstract
Abstract A bipolar semiconductor is manufactured by forming a plurality of grooves along the vertical (111) planes in a high resistivity epitaxial silicon layer which is disposed on an N+ (110) oriented substrate. Low resistivity epitaxial silicon of the same conductivity type is then used to fill in the grooves, thus forming alternate vertical regions of high and low resistivity. A base region is then diffused into said epitaxial layer and a plurality of emitters regions are diffused into said base region at locations directly above the low resistivity epitaxial regions.
Inventors
- 👤 Alan L. Harrington
- 👤 Richard Allison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 02:14
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/137; H10D62/133; H10P; H10P14/00; H10P14/20; H10P14/27; H10P14/271; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/3466; Y; Y10; Y10S; Y10S148/00; Y10S148/026; Y10S148/088
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
131 words
A method for manufacturing a semiconductor device comprising the steps of: forming a plurality of grooves through a high resistivity silicon layer which is disposed on a highly doped silicon substrate of the same type conductivity as said high resistivity silicon layer; filling said grooves with low resistivity silicon of the same type conductivity as said substrate such that alternating regions of high and low resistivity extend upward from said substrate; diffusing dopant of a type opposite to that of said substrate partially into said high and low resistivity regions to form the base of said semiconductor device; diffusing dopant of a type opposite to that of said base into said base at a plurality of discrete locations which are above said low resistivity regions, thus forming a plurality of emitters.
Claim 2
Independent Claim
131 words
A method for manufacturing a semiconductor device comprising the steps of: forming a plurality of grooves through a high resistivity silicon layer which is disposed on a highly doped silicon substrate of the same type conductivity as said high resistivity silicon layer; filling said grooves with low resistivity silicon of the same type conductivity as said substrate such that alternating regions of high and low resistivity extend upward from said substrate; diffusing dopant of a type opposite to that of said substrate partially into said high and low resistivity regions to form the base of said semiconductor device; diffusing dopant of a type opposite to that of said base into said base at a plurality of discrete locations which are above said low resistivity regions, thus forming a plurality of emitters.
Claim 3
Dependent Claim
22 words
The method according to claim 1 wherein the top surface of the high resistivity silicon layer lies in the (110) crystalline plane.
Claim 4
Dependent Claim
38 words
The method according to claim 2 wherein the grooves are aligned such that the edges of said grooves are defined by the (111) crystalline planes which lie perpendicular to the (110) surface of the high resistivity silicon layer.
Claim 5
Dependent Claim
19 words
The method according to claim 1 wherein the resistivity of said high resistivity silicon layer is approximately 100 ohms/cm.
Claim 6
Dependent Claim
18 words
The method according to claim 4 wherein the resistivity of said low resistivity silicon is approximately 1 ohm/cm.
Claim 7
Dependent Claim
15 words
The method according to claim 1 wherein said semiconductor device is a bipolar power transistor.
Claim 8
Dependent Claim
37 words
The method according to claim 1 wherein the depth of diffusion of said base is approximately 0.3 to 0.5 microns and the total depth of the high and low resistivity layers is approximately 0.6 to 1.5 microns.
Claim 9
Dependent Claim
23 words
The method according to claim 1 wherein the base is disposed such that the sides of said base are within high resistivity regions.
Claim 10
Dependent Claim
30 words
The method according the claim 1 wherein the substrate, the emitters and the high and low resistivity regions are all of N-type conductivity and the base is of P-type conductivity.
Claim 11
Dependent Claim
13 words
The method according to claim 1 wherein the grooves are formed by etching.
Claim 12
Dependent Claim
47 words
The method according to claim 1 wherein the layer disposed on said substrate is of low resistivity silicon instead of high resistivity silicon, grooves are formed in said low resistivity layer and high resistivity silicon instead of low resistivity silicon is used to fill in said grooves.
Claim 13
Dependent Claim
17 words
The method according to claim 1 wherein said high and low resistivity silicon layers are epitaxial silicon.
Claim 14
Independent Claim
138 words
A method for manufacturing a semiconductor device comprising the steps of: forming a plurality of grooves through a silicon layer of one type conductivity and resistivity which is disposed on a highly doped silicon substrate of the same type conductivity as said silicon layer; and filling said grooves with silicon of the same type conductivity as said silicon layer but with different resistivity than said silicon layer such that alternating high and low resistivity regions result; diffusing dopant of a conductivity type opposite to that of said substrate partially into said high and low resistivity regions to form the base of said semiconductor device; diffusing dopant of a type opposite to that of said base into said base at a plurality of discrete locations which are above the regions of lower resistivity, thus forming a plurality of emitters.
Claim 15
Independent Claim
138 words
A method for manufacturing a semiconductor device comprising the steps of: forming a plurality of grooves through a silicon layer of one type conductivity and resistivity which is disposed on a highly doped silicon substrate of the same type conductivity as said silicon layer; and filling said grooves with silicon of the same type conductivity as said silicon layer but with different resistivity than said silicon layer such that alternating high and low resistivity regions result; diffusing dopant of a conductivity type opposite to that of said substrate partially into said high and low resistivity regions to form the base of said semiconductor device; diffusing dopant of a type opposite to that of said base into said base at a plurality of discrete locations which are above the regions of lower resistivity, thus forming a plurality of emitters.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-05-10 | 1985-11-09 | 1986-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-05-10 | 1989-11-09 | 1990-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-05-10 | 1993-11-09 | 1994-05-11 | $7700.00 | Window Closed / Lapsed |